ROM_CTRL/64KB Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	14.530s	3.635ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	23.450s	2.827ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.350s	4.952ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.410s	661.556us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.140s	1.128ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.300s	1.347ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.350s	4.952ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	1.128ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.410s	3.787ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.900s	2.254ms	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	14.220s	274.228us	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	55.600s	1.042ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.640s	8.217ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.190s	1.047ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	28.510s	3.821ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	28.510s	3.821ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	23.450s	2.827ms	5	5	100.00
		rom_ctrl_csr_rw	15.350s	4.952ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	1.128ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.190s	362.705us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	23.450s	2.827ms	5	5	100.00
		rom_ctrl_csr_rw	15.350s	4.952ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.140s	1.128ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	20.190s	362.705us	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	2.039m	12.171ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.490m	1.020ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.245m	1.663ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.490m	1.020ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.490m	1.020ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.490m	1.020ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	14.530s	3.635ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	14.530s	3.635ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	14.530s	3.635ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.245m	1.663ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.640s	8.217ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.672m	82.653ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	2.039m	12.171ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.490m	1.020ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	4.096m	9.308ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.47	96.89	92.13	97.68	100.00	98.62	97.90	99.06

Failure Buckets

• UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 2 failures.

    • 21.rom_ctrl_stress_all_with_rand_reset.73438721130539648372069882753570676713078974598700310570670714478811012632101
      Line 109, in log /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 4424522036 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 4424522036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.rom_ctrl_stress_all_with_rand_reset.107908879831942921655126863333785033980504042706305551626840287180366054066218
      Line 81, in log /workspaces/repo/scratch/os_regression_2024_09_08/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1267781846 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
        UVM_INFO @ 1267781846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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