ROM_CTRL/64KB Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	24.410s	1.034ms	10	10	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	21.800s	265.168us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	20.300s	2.362ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.130s	915.812us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.490s	1.540ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.980s	1.642ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	20.300s	2.362ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.490s	1.540ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.520s	564.359us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.240s	711.300us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	21.440s	1.070ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.401m	4.252ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	44.650s	7.858ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	18.140s	1.030ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	26.080s	12.237ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	26.080s	12.237ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	21.800s	265.168us	5	5	100.00
		rom_ctrl_csr_rw	20.300s	2.362ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.490s	1.540ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	21.530s	3.946ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	21.800s	265.168us	5	5	100.00
		rom_ctrl_csr_rw	20.300s	2.362ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.490s	1.540ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	21.530s	3.946ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.185m	1.065ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.933m	1.166ms	5	5	100.00
		rom_ctrl_tl_intg_err	3.464m	596.423us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.933m	1.166ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.933m	1.166ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.933m	1.166ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	24.410s	1.034ms	10	10	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	24.410s	1.034ms	10	10	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	24.410s	1.034ms	10	10	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	3.464m	596.423us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
		rom_ctrl_kmac_err_chk	44.650s	7.858ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.288m	19.181ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.185m	1.065ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.933m	1.166ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.658m	21.529ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			458	460	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.42	96.89	91.99	97.68	100.00	98.28	98.05	99.06

Failure Buckets

UVM_FATAL sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.rom_ctrl_stress_all_with_rand_reset.63613883278941029292986921044575182517370684398665971091398745502024753102043
    Line 92, in log /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1396862419 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 1396862419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.rom_ctrl_stress_all_with_rand_reset.12756134547736340527555892921753041446239844727806768066887673463931454839632
    Line 120, in log /workspaces/repo/scratch/os_regression_2024_09_03/rom_ctrl_64kB-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2704459441 ps: uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.sequencer [SEQDEFPRI] Sequence m_tl_host_base_seq has illegal priority: -1
  UVM_INFO @ 2704459441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/64KB Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`