18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.360s | 773.382us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.040s | 116.612us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.980s | 147.542us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 7.910s | 2.082ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.880s | 140.796us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 10.220s | 3.477ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.160s | 2.040ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.144m | 42.684ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 22.140s | 5.950ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 7.540s | 6.417ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 4.980s | 2.161ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.110s | 135.802us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.760s | 355.092us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.000s | 364.934us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.350s | 532.895us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.800s | 42.679us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0.700s | 50.079us | 0 | 2 | 0.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 2.090s | 449.337us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.770s | 24.259us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.820s | 173.606us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.110s | 135.802us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.880s | 20.681us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.680s | 1.753ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.490s | 642.346us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.178m | 16.657ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.279m | 27.098ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.650s | 4.254ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.279m | 27.098ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.490s | 642.346us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.770s | 49.964us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.700s | 32.177us | 5 | 5 | 100.00 |
| V1 | TOTAL | 158 | 161 | 98.14 | |||
| V2 | idcode | rv_dm_smoke | 1.360s | 773.382us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.340s | 191.727us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.426m | 50.000ms | 0 | 2 | 0.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.870s | 282.088us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 6.230s | 1.681ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 7.560s | 4.695ms | 2 | 20 | 10.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 5.890s | 3.052ms | 1 | 20 | 5.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 34.240s | 18.438ms | 1 | 20 | 5.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.200s | 170.883us | 1 | 2 | 50.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.930s | 423.965us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.860s | 55.726us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 3.630s | 3.158ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 2.238m | 50.000ms | 12 | 40 | 30.00 | ||
| V2 | stress_all | rv_dm_stress_all | 2.201h | 10.000s | 1 | 50 | 2.00 |
| V2 | alert_test | rv_dm_alert_test | 0.790s | 22.370us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.470s | 404.323us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.470s | 404.323us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.279m | 27.098ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.680s | 1.753ms | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.490s | 642.346us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.190s | 2.146ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.279m | 27.098ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.680s | 1.753ms | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.490s | 642.346us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.190s | 2.146ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 120 | 276 | 43.48 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.730s | 302.849us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.430s | 4.188ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.390m | 11.377ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 303 | 512 | 59.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 26 | 92.86 |
| V2 | 18 | 16 | 8 | 44.44 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 79.06 | 93.76 | 79.12 | 87.53 | 74.36 | 82.50 | 98.52 | 37.64 |
UVM_ERROR (rv_dm_scoreboard.sv:250) [scoreboard] Check failed sba_item.rdata[*] == data (* [*] vs * [*]) has 41 failures:
0.rv_dm_sba_tl_access.23566865424340865703543895268253047118358817835087584529884159847859714397629
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 1427173739 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 46526 [0xb5be])
SBA item:
item: (sba_access_item@27109) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'h50929f5e wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@27071) { a_addr: 'h50929f5c a_data: 'hf6a90000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h276bb d_param: 'h0 d_source: 'h0 d_data: 'hb5be9ae3 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd3b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_sba_tl_access.90235879951864756205855088711547903304951679627835260677470096900509070511852
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 152843999 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 582206805 [0x22b3c555])
SBA item:
item: (sba_access_item@7077) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'hc2db7fc0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7021) { a_addr: 'hc2db7fc0 a_data: 'hb544 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27e8a d_param: 'h0 d_source: 'h0 d_data: 'h22b3c555 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd56 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 15 more failures.
0.rv_dm_delayed_resp_sba_tl_access.7925091943068850552671360611861567387302020260888657819584361999887850474256
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 273046819 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 32155 [0x7d9b])
SBA item:
item: (sba_access_item@6735) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'h6b454df6 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6645) { a_addr: 'h6b454df4 a_data: 'hda520000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24868 d_param: 'h0 d_source: 'h0 d_data: 'h7d9b139e d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd0c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_delayed_resp_sba_tl_access.57411774682287625413269262717600185421827932618378380160716606325445364729848
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 149258259 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2753834642 [0xa4242e92])
SBA item:
item: (sba_access_item@10177) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h97334d40 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@10121) { a_addr: 'h97334d40 a_data: 'h8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2491e d_param: 'h0 d_source: 'h0 d_data: 'ha4242e92 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd16 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 14 more failures.
1.rv_dm_bad_sba_tl_access.8957695458995211546319210138350333113515146852304484095530756754981462314239
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 578169697 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1173803581 [0x45f6d23d])
SBA item:
item: (sba_access_item@9057) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h972674f4 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@9001) { a_addr: 'h972674f4 a_data: 'h7e9d6990 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27421 d_param: 'h0 d_source: 'h0 d_data: 'h45f6d23d d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd52 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
15.rv_dm_bad_sba_tl_access.83362382729724534190696254269876172334020995829564195935066168161966784381612
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 24684482 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 107 [0x6b])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h7cd1b4ab wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrBadAddr timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h7cd1b4a8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24daa d_param: 'h0 d_source: 'h0 d_data: 'h6b1e2ff9 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heca a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 2 more failures.
10.rv_dm_autoincr_sba_tl_access.71170670521251553390314693254127399198451708108826768929718978097504485791634
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 40231205 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 123855356 [0x761e1fc])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h761e1fc d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'hef3 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
13.rv_dm_autoincr_sba_tl_access.97515858804405026988234367064166598354143058593274143935648475826282024264702
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 37790742 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2602418588 [0x9b1dc19c])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h9b1dc19c d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd1f a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 2 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 21 failures:
Test rv_dm_bad_sba_tl_access has 12 failures.
0.rv_dm_bad_sba_tl_access.25258577517246409390591430027028733376729438087959572996297409435586748830901
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 120912765 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 120912765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_bad_sba_tl_access.36432832517688815798165398941608357484818507802011730961611622447459911164197
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 50578498 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 50578498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Test rv_dm_autoincr_sba_tl_access has 7 failures.
0.rv_dm_autoincr_sba_tl_access.66464158569423015806035891141728061177784910264144150697014185116967291835869
Line 284, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 220337138 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 4 [0x4])
UVM_INFO @ 220337138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_autoincr_sba_tl_access.28309333670798102577229250002662816015069951623011012810433611398389798178607
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 50924877 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 50924877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test rv_dm_sba_tl_access has 1 failures.
15.rv_dm_sba_tl_access.89196243025690296685823833449525399759110983673968103626395190000691207062650
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 129923755 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (3 [0x3] vs 0 [0x0])
UVM_INFO @ 129923755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
19.rv_dm_delayed_resp_sba_tl_access.19279032993685237406187165975247993004652549859613867838688159985244926585831
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 159941242 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (3 [0x3] vs 0 [0x0])
UVM_INFO @ 159941242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 20 failures:
1.rv_dm_stress_all.29651916623729036418309763975664847306256711726991793291706224749809155142327
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9929561 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (4294964223 [0xfffff3ff] vs 4209 [0x1071])
UVM_INFO @ 9929561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all.26743891483903465134580069545338441585000305786230440484228811912311325084338
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 94839014 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 94839014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
1.rv_dm_stress_all_with_rand_reset.18017628234383160642237508628031665743782491990968742890009424936275692554362
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55665310 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 55665310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.15931807821205999684244987475966174035599057292020742247496630040868727931205
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 788801331 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 788801331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:91) m_jtag_dmi_monitor [m_jtag_dmi_monitor] JTAG operation * != DmiOpNone in quiet period has 17 failures:
Test rv_dm_halt_resume_whereto has 2 failures.
0.rv_dm_halt_resume_whereto.105832058468640417750703610546076625293253057159214485759734456826714621323395
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 50078892 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 50078892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_halt_resume_whereto.56434424938506010829764553526923359096949191903561718649538706078565696386851
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 58492420 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 58492420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 5 failures.
3.rv_dm_stress_all_with_rand_reset.28508463504318007325054347705428108667072003214690156757046435750519625215763
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 121638454 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 121638454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all_with_rand_reset.91851952511431058515304928064722855240132655761446464303214393039996826358989
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25564260 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 25564260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test rv_dm_stress_all has 10 failures.
4.rv_dm_stress_all.73765001084287413156318060858806035765497615392292474558083453429967117515407
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 48957406 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 48957406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all.88666631327422040676124534266026359634870935739500528333550909772988309292736
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14919825 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 14919825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 15 failures:
Test rv_dm_stress_all_with_rand_reset has 6 failures.
0.rv_dm_stress_all_with_rand_reset.93587171190707435406423118793094559615672202058807616828155845332478281339455
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 270693852 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 1051879299 [0x3eb26783])
UVM_INFO @ 270693852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.46806590164442182198054247369761527322069916823994229444810774365507451488369
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 50116540 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3740990222 [0xdefafb0e])
UVM_INFO @ 50116540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
1.rv_dm_jtag_dmi_debug_disabled.12190297449616224450366344316855350289354895446960932328998690014355581091975
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 24348279 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3763217616 [0xe04e24d0])
UVM_INFO @ 24348279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 8 failures.
9.rv_dm_stress_all.104595210584467963103310656900343703561956993953538583042885200743618504283150
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 157832040 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 1254330477 [0x4ac3906d])
UVM_INFO @ 157832040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all.11535686985107716538762705641930476295478692130832695731699853330628103939457
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 39087541 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 2653558568 [0x9e2a1728])
UVM_INFO @ 39087541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 11 failures:
1.rv_dm_tap_fsm_rand_reset.105187930010814657970219795269689804870497666593000963830891587509967415810315
Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 6350757133 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6350757133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_tap_fsm_rand_reset.19952450031899343361514310915023370602870908358256261078941359925141588176518
Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 12419826892 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12419826892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 7 failures:
5.rv_dm_tap_fsm_rand_reset.46830987249389426651776733835450376607805057022367251751694634493597237001096
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 6252834382 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6252834382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_tap_fsm_rand_reset.66917905750026512468470618994318684787545754800029005741976645660319811093180
Line 398, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 16298953907 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 16298953907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
Test rv_dm_jtag_dtm_idle_hint has 2 failures.
0.rv_dm_jtag_dtm_idle_hint.96215585265792751524601165535427533698487779766323626348684369672188674409934
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dtm_idle_hint.60279164271291303606488657721585511586187487271640066845531329439293600161421
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_csr_bit_bash has 1 failures.
2.rv_dm_csr_bit_bash.95567201842272176567824202480701182689198713072034640353860465002538248583243
Line 317, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_tap_fsm_rand_reset has 1 failures.
3.rv_dm_tap_fsm_rand_reset.72368142573707690490987248417476040410671300061122851899274935411766764152230
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
24.rv_dm_stress_all.104062390361065187469134657881816051327599032155927852253235494069279228889123
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*]) has 5 failures:
3.rv_dm_stress_all.8729861498820030395477377813532497430155510958565351928112605114454532466127
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5770833005 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5770833005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all.41352825114792039179376355634308073808936658523236359612422568649802255954434
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5263912635 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5263912635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 5 failures:
9.rv_dm_stress_all_with_rand_reset.11637407175825057901406329582795898038990745522819754124648705140478249516996
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2601480003 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xec012100)
UVM_INFO @ 2601480003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.rv_dm_stress_all_with_rand_reset.113321987720270572646933731608974258269238521008443905215328047584625463814233
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3731831521 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x6f4ad100)
UVM_INFO @ 3731831521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 5 failures:
18.rv_dm_stress_all_with_rand_reset.10680315731095904617044134245342734668198004752819919515983178923985175435467
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4932529 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 4932529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.21673657769977072474208998849398848683552721793621186522930573482698279736076
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4211331 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 4211331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
27.rv_dm_stress_all.65143020697542542197178183755760324296004143975156700620546511378672137006792
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8767247 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 8767247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all.22055284688369172491748407142141691281469009874738926913436294784302597974858
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 13844498 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 13844498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:282) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (* [*] vs * [*]) has 4 failures:
Test rv_dm_autoincr_sba_tl_access has 2 failures.
1.rv_dm_autoincr_sba_tl_access.54638746081799808568859059888789212171733742492084646142101725864732773135996
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 66335832 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 66335832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_autoincr_sba_tl_access.93219339449102181022993572722761096078168707899733109434262059578116365026786
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 36591071 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 36591071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 2 failures.
3.rv_dm_bad_sba_tl_access.84297930409907111978172626567000184227756745299803431391459077282257811436631
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 57211606 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 57211606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_bad_sba_tl_access.41129878436532545025490941886515546710169397120157129770247997781827983500518
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 30084453 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 30084453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:280) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (* [*] vs * [*]) has 4 failures:
4.rv_dm_autoincr_sba_tl_access.80724334548836095875297687622044609332372031576345731369955303643268953347196
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 78704742 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 78704742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_autoincr_sba_tl_access.69428295939439443836949944009104538280615565814613775921377972942112065856691
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 260374718 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 260374718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
19.rv_dm_bad_sba_tl_access.31567536913103011466465817546829363663628644138611174091137631255811235260301
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 47722152 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 47722152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 4 failures:
27.rv_dm_stress_all_with_rand_reset.16596580173230027162996294062132117691670686538293755650313392280566825096302
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 821335208 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 821335208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.rv_dm_stress_all_with_rand_reset.20302156830528379703864075030412156152814476038283654251576938368764118484046
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43160702 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 43160702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:
4.rv_dm_tap_fsm_rand_reset.61040165397455348567660481862580962574379762787619126644937120823805474623268
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 3271804211 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3271804211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_tap_fsm_rand_reset.79435604218682095470227945564177594577093841478383064987085688256240036242605
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 717343811 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 717343811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 3 failures:
4.rv_dm_stress_all_with_rand_reset.78686135451319342816079133955063057593462910057643629114000075818110508582361
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 106582726 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 106582726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_stress_all_with_rand_reset.17510374163825509358191473289560759430830394432035975078299042353452993294110
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1664047475 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1664047475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
5.rv_dm_stress_all_with_rand_reset.85218504958214135671155678232154831356743001771446511664563073948497997776274
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 200362947 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (0 [0x0] vs 65024 [0xfe00])
UVM_INFO @ 200362947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.rv_dm_stress_all_with_rand_reset.45828479582389147588672979493720144208965933562647280876333358913144268065336
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77503382 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (2 [0x2] vs 127155714 [0x7943e02])
UVM_INFO @ 77503382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
31.rv_dm_stress_all.95540053506204043789273716880014862596366761092316583655284744359928110546352
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 42570030 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (9 [0x9] vs 0 [0x0])
UVM_INFO @ 42570030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
6.rv_dm_stress_all_with_rand_reset.50240427933077038116424589132874228442725953159945174777612134464451824441461
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 35757856 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 35757856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all_with_rand_reset.90024413832927753418473924008964786379939130193493126493699037094468758069567
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12918445 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 12918445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all has 1 failures.
7.rv_dm_stress_all.26675947660974224728869084260116554266793536019317464256759979170148321788607
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1774180979 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 1774180979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
16.rv_dm_stress_all_with_rand_reset.1101242949682128360670066196890177618832858414434711068477573744138626814142
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5123183581 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 5123183581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all_with_rand_reset.56706118649444880567697581574810302865754328713891109073186954085191720314577
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 850755750 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 850755750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 3 failures:
17.rv_dm_stress_all_with_rand_reset.66010601482921995944307593438917437856745510218454819496875435519011119026952
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 223529464 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 3514083826 [0xd174a9f2]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 223529464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_stress_all_with_rand_reset.56660914921313121578973886456923123398706358114626360321526428326843215581783
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1042937367 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1484011873 [0x58743961]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 1042937367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 3 failures:
18.rv_dm_tap_fsm_rand_reset.76656650420173251683270212991410233650712990796290825820796847396227589122052
Line 277, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1832220794 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1832220794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_tap_fsm_rand_reset.79817378894483323592533147704799824870946517783245935168977423232000123943159
Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 7601662447 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7601662447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 3 failures:
18.rv_dm_stress_all.1821393425283809682021128370121683162669803374919555752176625207794822190349
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6374607517 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 6374607517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all.100790210871338821047023809589424491670182692969541948393168531905563969119382
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10739965827 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 10739965827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:275) [scoreboard] Check failed byte_mask == sba_tl_item.a_mask (* [*] vs * [*]) has 2 failures:
3.rv_dm_autoincr_sba_tl_access.58483771587354624631368566056336247558530605385834063884792018382019949359457
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 152459745 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@6081) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h6c0c3084 wdata: { [0]: 'ha463346 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6025) { a_addr: 'h6c0c3084 a_data: 'ha463346 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h27487 d_param: 'h0 d_source: 'h0 d_data: 'h6309623d d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1cb2 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
12.rv_dm_autoincr_sba_tl_access.83488607458294687606844351595085485154627656725013374736189762542696839541767
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 60079689 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (4 [0x4] vs 12 [0xc])
SBA item:
item: (sba_access_item@5665) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hdf65eb4a wdata: { [0]: 'h64ed0eda } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5627) { a_addr: 'hdf65eb48 a_data: 'heda0000 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h24851 d_param: 'h0 d_source: 'h0 d_data: 'h60212b0b d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1cbf a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
10.rv_dm_stress_all_with_rand_reset.59738266028028260083379071262081523033877806669973189309828491980190530913060
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111008176 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (6 [0x6] vs 18 [0x12])
UVM_INFO @ 111008176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all_with_rand_reset.70933042728312450341078464424031178185620117369394411713462338476850090184427
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 991205797 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 8904065 [0x87dd81])
UVM_INFO @ 991205797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 2 failures:
11.rv_dm_stress_all_with_rand_reset.24594872397925834098444313864070949622938742212391227421711875163302923809056
Line 296, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11376874983 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 11376874983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all_with_rand_reset.76203457427591150646667926765353727421789963342921351242271874144765212288120
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 115594027 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 115594027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 2 failures:
21.rv_dm_tap_fsm_rand_reset.83316668727072475485449319914423146332873239423293757964667005703281782328142
Line 337, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 12391834578 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 12391834578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.rv_dm_tap_fsm_rand_reset.78739773798644372081679634856670912982670322481079868614424011055360166810714
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 13143494702 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 13143494702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_* (addr=*) has 1 failures:
0.rv_dm_stress_all.88823636989705990299812273118557745651637979572263653646588842569583654298686
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2764985937 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_0 (addr=0xeabe6380)
UVM_INFO @ 2764985937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:67) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * } has 1 failures:
5.rv_dm_delayed_resp_sba_tl_access.107654477569684714988294734140450369811384789955881079960294034618630557352496
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 1958917 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1958917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6581) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
6.rv_dm_sba_tl_access.90235848589400540028041143138924180842252912269588118786802227102219479972912
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 180511849 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6581) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hf6b6127 wdata: { [0]: 'hd26a9f39 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 180511849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:260) [scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (* [*] vs * [*]) has 1 failures:
8.rv_dm_sba_tl_access.90018978214788510225158051895344460344326830843194143134091529386371979631144
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 164182638 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@6681) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h6d299854 wdata: { [0]: 'he7509f1e } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6525) { a_addr: 'h6d299854 a_data: 'h43738 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27560 d_param: 'h0 d_source: 'h0 d_data: 'hf40ee9f4 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd38 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (sba_access_monitor.sv:173) [m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (* << size)}) has 1 failures:
11.rv_dm_autoincr_sba_tl_access.57409741285100960327550546338952744356014741235401135406750294686062933430901
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 223073002 ps: (sba_access_monitor.sv:173) [uvm_test_top.env.m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (1 << size)})
UVM_INFO @ 223073002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
12.rv_dm_stress_all.13785923509742608644055982077273905014376384573241086054959247280858559393751
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 31882957 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 31882957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:183) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all_with_rand_reset.71397763696786993184629915373974886486441417867378228473824379688004552859844
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2672047138 ps: (rv_dm_base_vseq.sv:183) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 2672047138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 1 failures:
15.rv_dm_tap_fsm_rand_reset.63061352830402447003787193012860080689173324194644452784158562511721240630179
Line 327, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 14064167401 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14064167401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
15.rv_dm_stress_all.66113181272363564247485599296672392527629869609318093940675188220101193425917
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 25343792 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25343792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 1 failures:
29.rv_dm_stress_all.99143041732579424188982052758205482361125712346690773659275199128190093176916
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14015464451 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 14015464451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
31.rv_dm_stress_all_with_rand_reset.71902824593538327220354607442786376660749874838497752558884225382195441766614
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 149302430 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 149302430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
41.rv_dm_stress_all.81452099378391356051022303391209578364094793677321659184263831376940238784826
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 21475584 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21475584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:39) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
47.rv_dm_stress_all_with_rand_reset.93018711596566845581482020331808467481038494298665978415097649048317552929178
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45085202 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45085202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---