RV_DM Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.450s 478.149us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.790s 92.064us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.940s 95.616us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.590s 2.398ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.140s 143.646us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.230s 1.699ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.780s 1.962ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.945m 49.200ms 4 5 80.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 16.810s 45.800ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 16.580s 4.879ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 3.130s 724.899us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.250s 336.612us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.980s 401.174us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.880s 314.588us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.470s 262.724us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.870s 83.490us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.750s 24.543us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.630s 482.358us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.760s 27.390us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.900s 64.951us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.250s 336.612us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.810s 177.890us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.570s 1.243ms 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.490s 314.625us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.150m 9.801ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.230m 13.438ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.730s 3.899ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.230m 13.438ms 5 5 100.00
rv_dm_csr_rw 2.490s 314.625us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.720s 29.032us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 16.000us 5 5 100.00
V1 TOTAL 158 161 98.14
V2 idcode rv_dm_smoke 1.450s 478.149us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.380s 246.517us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.101m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.930s 79.355us 2 2 100.00
V2 sba rv_dm_sba_tl_access 2.550s 1.890ms 2 20 10.00
rv_dm_delayed_resp_sba_tl_access 3.480s 2.291ms 1 20 5.00
V2 bad_sba rv_dm_bad_sba_tl_access 31.130s 50.000ms 1 20 5.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 26.350s 50.000ms 1 20 5.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.780s 31.582us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 3.230s 774.174us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.830s 212.880us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 5.310s 2.498ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.244m 50.000ms 15 40 37.50
V2 stress_all rv_dm_stress_all 24.860s 7.334ms 4 50 8.00
V2 alert_test rv_dm_alert_test 0.800s 20.349us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.970s 167.505us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.970s 167.505us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.230m 13.438ms 5 5 100.00
rv_dm_csr_hw_reset 2.570s 1.243ms 5 5 100.00
rv_dm_csr_rw 2.490s 314.625us 20 20 100.00
rv_dm_same_csr_outstanding 8.660s 2.315ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.230m 13.438ms 5 5 100.00
rv_dm_csr_hw_reset 2.570s 1.243ms 5 5 100.00
rv_dm_csr_rw 2.490s 314.625us 20 20 100.00
rv_dm_same_csr_outstanding 8.660s 2.315ms 20 20 100.00
V2 TOTAL 126 276 45.65
V2S tl_intg_err rv_dm_sec_cm 1.570s 282.918us 5 5 100.00
rv_dm_tl_intg_err 20.620s 2.715ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 21.200s 6.590ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 309 512 60.35

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.45 93.81 79.26 87.53 71.79 82.67 98.52 35.57

Failure Buckets

Past Results