RV_DM Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	9.040s	3.258ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.920s	908.217us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.180s	621.795us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.857m	60.806ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.210s	1.486ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	18.130s	7.502ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	38.360s	14.249ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.449m	79.524ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	10.095m	209.498ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.260s	985.856us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.680s	408.058us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	4.620s	5.734ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.970s	857.214us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	4.310s	1.490ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.770s	1.808ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.780s	107.308us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.870s	787.355us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.410s	985.827us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.950s	87.790us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.310s	588.178us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	4.620s	5.734ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.030s	142.509us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.020s	400.115us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.760s	204.639us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.166m	6.509ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.236m	6.938ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	6.560s	2.950ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.236m	6.938ms	5	5	100.00
		rv_dm_csr_rw	2.760s	204.639us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.030s	131.335us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.910s	102.221us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	9.040s	3.258ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.450s	2.887ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.980s	116.069us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.430s	1.042ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	13.050s	4.599ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	18.470s	11.430ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	15.000s	5.275ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.205m	93.720ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	4.190s	1.538ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.660s	788.397us	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.840s	480.027us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.190s	187.049us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	27.950s	11.624ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.157m	40.220ms	9	10	90.00
V2	stress_all	rv_dm_stress_all	44.520s	18.854ms	42	50	84.00
V2	alert_test	rv_dm_alert_test	1.090s	123.560us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.500s	535.110us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.500s	535.110us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.236m	6.938ms	5	5	100.00
		rv_dm_csr_hw_reset	3.020s	400.115us	5	5	100.00
		rv_dm_csr_rw	2.760s	204.639us	20	20	100.00
		rv_dm_same_csr_outstanding	8.220s	1.088ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.236m	6.938ms	5	5	100.00
		rv_dm_csr_hw_reset	3.020s	400.115us	5	5	100.00
		rv_dm_csr_rw	2.760s	204.639us	20	20	100.00
		rv_dm_same_csr_outstanding	8.220s	1.088ms	20	20	100.00
V2		TOTAL			239	248	96.37
V2S	tl_intg_err	rv_dm_sec_cm	2.590s	595.583us	5	5	100.00
		rv_dm_tl_intg_err	27.520s	4.617ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	27.520s	4.617ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.660s	788.397us	2	2	100.00
		rv_dm_debug_disabled	0.940s	157.242us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	23.790s	2.243ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			442	461	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	15	83.33
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.82	95.27	79.45	89.42	74.36	85.50	98.42	57.31

Failure Buckets

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 6 failures:

Test rv_dm_stress_all_with_rand_reset has 3 failures.

3.rv_dm_stress_all_with_rand_reset.39208971884317463464757313655597900768794420431906179014828111787703287716278
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1568095859 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1568095859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.rv_dm_stress_all_with_rand_reset.102395034071411069558206437616849818620795123073484361857002268009244270888943
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1915513365 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1915513365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_dm_stress_all has 3 failures.

13.rv_dm_stress_all.51891294093538884587361920075970994652706156157884048948146065222828312112799
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2280761540 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 2280761540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.rv_dm_stress_all.9630617214208938426541275881413609997408472070872237354589622816255630995811
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 4260264386 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 4260264386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 5 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.
- 1.rv_dm_stress_all_with_rand_reset.35015596490247589603856968373558401036038665699069936223322502869386957197516
  Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 1595010249 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1595010249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test rv_dm_stress_all has 4 failures.

10.rv_dm_stress_all.4835805559353799406697396690634053378809657296447548063829198400527254544491
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 1644963863 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1644963863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rv_dm_stress_all.61394330077611897887681582670566454679041837339695354155710895250396094254834
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 4173391916 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 4173391916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 5.rv_dm_stress_all_with_rand_reset.38947115219010004076070803922309344955043120391722268336785751400609359479847
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1948647471 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 1948647471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all_with_rand_reset.93249121604607540190522867784185177819463675601369375588484305571473801685794
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3753379637 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 3753379637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:25) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.14075465553136977378635790062705090865863027032437246044899141562412252068372
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2242583025 ps: (rv_dm_halt_resume_whereto_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2242583025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 1.rv_dm_stress_all.55504675542806785546866348406713200000085538965192005962658348927183165345317
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 6012361417 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 6012361417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.49948207294374659957434281791866889556264139492836460857729205896681910963892
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 628309224 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 628309224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.38628457617360752233014435684402713326468693926916832307753845400021183781830
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 578563140 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 64 [0x40])
  UVM_INFO @ 578563140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 5.rv_dm_tap_fsm_rand_reset.491294523300947505351234553734540157537198268307537171450331532502546437127
    Line 387, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 77061775124 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 77061775124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:30) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.32453953124000699957291904982430135628900423775492349139234333921744296470236
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3401538431 ps: (rv_dm_mem_tl_access_halted_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3401538431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```