RV_DM Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 9.040s 3.258ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.920s 908.217us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.180s 621.795us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 2.857m 60.806ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.210s 1.486ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 18.130s 7.502ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 38.360s 14.249ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.449m 79.524ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 10.095m 209.498ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.260s 985.856us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.680s 408.058us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 4.620s 5.734ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.970s 857.214us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 4.310s 1.490ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.770s 1.808ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.780s 107.308us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.870s 787.355us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.410s 985.827us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.950s 87.790us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.310s 588.178us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 4.620s 5.734ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.030s 142.509us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.020s 400.115us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.760s 204.639us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.166m 6.509ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.236m 6.938ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 6.560s 2.950ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.236m 6.938ms 5 5 100.00
rv_dm_csr_rw 2.760s 204.639us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.030s 131.335us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.910s 102.221us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 9.040s 3.258ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.450s 2.887ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.980s 116.069us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.430s 1.042ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 13.050s 4.599ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 18.470s 11.430ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 15.000s 5.275ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.205m 93.720ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 4.190s 1.538ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.660s 788.397us 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.840s 480.027us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.190s 187.049us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 27.950s 11.624ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.157m 40.220ms 9 10 90.00
V2 stress_all rv_dm_stress_all 44.520s 18.854ms 42 50 84.00
V2 alert_test rv_dm_alert_test 1.090s 123.560us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.500s 535.110us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.500s 535.110us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.236m 6.938ms 5 5 100.00
rv_dm_csr_hw_reset 3.020s 400.115us 5 5 100.00
rv_dm_csr_rw 2.760s 204.639us 20 20 100.00
rv_dm_same_csr_outstanding 8.220s 1.088ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.236m 6.938ms 5 5 100.00
rv_dm_csr_hw_reset 3.020s 400.115us 5 5 100.00
rv_dm_csr_rw 2.760s 204.639us 20 20 100.00
rv_dm_same_csr_outstanding 8.220s 1.088ms 20 20 100.00
V2 TOTAL 239 248 96.37
V2S tl_intg_err rv_dm_sec_cm 2.590s 595.583us 5 5 100.00
rv_dm_tl_intg_err 27.520s 4.617ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 27.520s 4.617ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.660s 788.397us 2 2 100.00
rv_dm_debug_disabled 0.940s 157.242us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 23.790s 2.243ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 442 461 95.88

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 15 83.33
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.82 95.27 79.45 89.42 74.36 85.50 98.42 57.31

Failure Buckets

Past Results