RV_DM Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 9.990s 4.141ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.760s 904.945us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.880s 1.215ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 41.990s 16.675ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.300s 1.655ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 41.890s 14.627ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 17.320s 6.747ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.923m 77.440ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 5.279m 119.633ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.070s 975.242us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.140s 364.796us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.320s 1.343ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.500s 1.946ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.540s 916.266us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.970s 536.216us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.150s 278.132us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.610s 1.639ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.260s 722.296us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.920s 200.062us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 4.030s 1.353ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.320s 1.343ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.960s 85.500us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.660s 213.560us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.680s 364.301us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.172m 61.055ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.115m 2.011ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.170s 4.172ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.115m 2.011ms 5 5 100.00
rv_dm_csr_rw 2.680s 364.301us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.790s 49.710us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.890s 89.310us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 9.990s 4.141ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.920s 980.423us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.810s 151.291us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.070s 338.113us 2 2 100.00
V2 sba rv_dm_sba_tl_access 14.100s 10.398ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 17.030s 6.105ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 48.140s 18.512ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.732m 37.540ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.140s 833.147us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.590s 1.801ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.730s 444.121us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.070s 149.140us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 11.160s 8.559ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.437m 47.339ms 6 10 60.00
V2 stress_all rv_dm_stress_all 42.810s 16.415ms 42 50 84.00
V2 alert_test rv_dm_alert_test 1.040s 122.944us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.760s 253.177us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.760s 253.177us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.115m 2.011ms 5 5 100.00
rv_dm_csr_hw_reset 2.660s 213.560us 5 5 100.00
rv_dm_csr_rw 2.680s 364.301us 20 20 100.00
rv_dm_same_csr_outstanding 8.260s 2.706ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.115m 2.011ms 5 5 100.00
rv_dm_csr_hw_reset 2.660s 213.560us 5 5 100.00
rv_dm_csr_rw 2.680s 364.301us 20 20 100.00
rv_dm_same_csr_outstanding 8.260s 2.706ms 20 20 100.00
V2 TOTAL 236 248 95.16
V2S tl_intg_err rv_dm_sec_cm 4.730s 1.536ms 5 5 100.00
rv_dm_tl_intg_err 29.490s 5.168ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 29.490s 5.168ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.590s 1.801ms 2 2 100.00
rv_dm_debug_disabled 1.020s 79.717us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 34.390s 3.263ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 439 461 95.23

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 15 83.33
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.58 95.32 80.00 89.42 74.36 85.67 98.32 54.99

Failure Buckets

Past Results