RV_DM Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.180s	1.846ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	5.010s	1.587ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.330s	720.597us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	54.960s	23.512ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.020s	1.700ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	59.060s	22.017ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	23.260s	9.596ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.161m	53.203ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.803m	96.481ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.060s	597.015us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.280s	762.830us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	5.900s	3.621ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	3.900s	4.471ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.890s	441.506us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.180s	1.078ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.180s	371.949us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.250s	532.904us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	3.080s	1.679ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.940s	78.716us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.320s	233.769us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	5.900s	3.621ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.080s	102.461us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.690s	399.577us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.690s	1.316ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.184m	10.202ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.564m	51.263ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	11.450s	5.334ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.564m	51.263ms	5	5	100.00
		rv_dm_csr_rw	2.690s	1.316ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.840s	70.824us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.830s	138.464us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.180s	1.846ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.510s	1.078ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.010s	106.126us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.370s	468.407us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	25.490s	9.330ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	30.500s	11.125ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	24.110s	12.433ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	7.950m	179.293ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	4.670s	1.530ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	8.200s	4.968ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.370s	254.553us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.760s	435.147us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.220s	5.315ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.181m	45.900ms	6	10	60.00
V2	stress_all	rv_dm_stress_all	24.790s	9.205ms	45	50	90.00
V2	alert_test	rv_dm_alert_test	1.020s	118.421us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.170s	1.540ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.170s	1.540ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.564m	51.263ms	5	5	100.00
		rv_dm_csr_hw_reset	2.690s	399.577us	5	5	100.00
		rv_dm_csr_rw	2.690s	1.316ms	20	20	100.00
		rv_dm_same_csr_outstanding	9.000s	1.941ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.564m	51.263ms	5	5	100.00
		rv_dm_csr_hw_reset	2.690s	399.577us	5	5	100.00
		rv_dm_csr_rw	2.690s	1.316ms	20	20	100.00
		rv_dm_same_csr_outstanding	9.000s	1.941ms	20	20	100.00
V2		TOTAL			239	248	96.37
V2S	tl_intg_err	rv_dm_sec_cm	6.610s	2.078ms	5	5	100.00
		rv_dm_tl_intg_err	22.970s	3.887ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	22.970s	3.887ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	8.200s	4.968ms	2	2	100.00
		rv_dm_debug_disabled	0.950s	103.270us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	3.040m	27.980ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			442	461	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	15	83.33
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.20	95.27	79.59	89.42	74.36	85.50	98.21	53.09

Failure Buckets

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 0.rv_dm_stress_all_with_rand_reset.21345044412890724520191353049672130018102417542353798051343778969287229540984
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 188837405 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 2 [0x2])
  UVM_INFO @ 188837405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.82182048786503285437016707449381213622403347377369758773739146372285478988511
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 145077654 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 145077654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 4 failures:

Test rv_dm_stress_all has 4 failures.

14.rv_dm_stress_all.50715762165280724746576056766395232852765391614383688509522969644417598256751
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 4143642089 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 4143642089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.rv_dm_stress_all.96218070595954051074003946738193815352666762643083079104138369222364511764753
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 1543137069 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1543137069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 2 failures:

Test rv_dm_tap_fsm_rand_reset has 2 failures.

1.rv_dm_tap_fsm_rand_reset.100511912728653904808177912947126288375016439134713814352149096784843393785054
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 19010486193 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 19010486193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.rv_dm_tap_fsm_rand_reset.35926522206918942638479128753512350981052145780717579272983059590213515732030
Line 333, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 33297599528 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2182966305 [0x821d6c21] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 33297599528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.22000413158365557271434970106199048459733981747878754044071529813715235120023
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1685522947 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1685522947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 41.rv_dm_stress_all.59093589562626420100001886847451638443062297460089843708590186602860695255757
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2251218880 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 2251218880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 5.rv_dm_stress_all_with_rand_reset.79377763612772291509750396591814295522909075372623799169150235458602102575694
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 350826997 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 350826997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all_with_rand_reset.41331179125507750719341800047954740154055591538443279526175588047373416413292
    Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 27980062946 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 27980062946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:28) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.50534889433645836256332715840869579859748093670442489378717020889138001573342
    Line 280, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7571824934 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 7571824934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:55) [rv_dm_halt_resume_whereto_vseq] Check failed (rdata inside {prog_buf_jal, abs_cmd_jal}) The whereto register reads as *, which is not either of the jumps we expected (600006f, *f) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.29766531268185004254132548157477351389320851443444569204825710527472331400745
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2607047651 ps: (rv_dm_halt_resume_whereto_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed (rdata inside {prog_buf_jal, abs_cmd_jal}) The whereto register reads as 1, which is not either of the jumps we expected (600006f, 380006f)
  UVM_INFO @ 2607047651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 8.rv_dm_tap_fsm_rand_reset.58056390885855567161320196796504159234346347174658363308576716115997584385450
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 538952758 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 538952758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 9.rv_dm_tap_fsm_rand_reset.101383383107317231730086220996544689237125285342040264790653455688249914170842
    Line 365, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 43464047478 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 43464047478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.5709311399426657238430777447576743137467420782245936353859858482238726641637
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 181439294 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (1769489 [0x1b0011] vs 0 [0x0])
  UVM_INFO @ 181439294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```