RV_DM Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.680s	2.167ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.060s	427.695us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.850s	457.188us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.306m	30.466ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.970s	1.266ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	17.730s	8.808ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	27.130s	9.824ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.502m	32.525ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.860m	92.224ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.960s	1.260ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.650s	781.997us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.920s	937.561us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.090s	548.378us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.470s	543.604us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.500s	1.017ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.760s	457.416us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.770s	1.825ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	15.440s	5.509ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.320s	600.138us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.420s	946.596us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.920s	937.561us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.930s	202.704us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.570s	363.401us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.650s	210.699us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.216m	10.186ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.259m	3.401ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.670s	3.816ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.259m	3.401ms	5	5	100.00
		rv_dm_csr_rw	2.650s	210.699us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.890s	171.514us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.810s	44.638us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	6.680s	2.167ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	7.370s	2.346ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.300s	189.677us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.160s	1.161ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	40.280s	15.607ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	33.980s	12.888ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	24.540s	7.870ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.392m	55.678ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	12.950s	4.541ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.560s	3.843ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.070s	787.517us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.610s	413.638us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.340s	3.771ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.623m	48.886ms	8	10	80.00
V2	stress_all	rv_dm_stress_all	39.990s	15.357ms	45	50	90.00
V2	alert_test	rv_dm_alert_test	1.100s	137.957us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.540s	363.567us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.540s	363.567us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.259m	3.401ms	5	5	100.00
		rv_dm_csr_hw_reset	2.570s	363.401us	5	5	100.00
		rv_dm_csr_rw	2.650s	210.699us	20	20	100.00
		rv_dm_same_csr_outstanding	8.110s	1.277ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.259m	3.401ms	5	5	100.00
		rv_dm_csr_hw_reset	2.570s	363.401us	5	5	100.00
		rv_dm_csr_rw	2.650s	210.699us	20	20	100.00
		rv_dm_same_csr_outstanding	8.110s	1.277ms	20	20	100.00
V2		TOTAL			240	248	96.77
V2S	tl_intg_err	rv_dm_sec_cm	2.970s	848.942us	5	5	100.00
		rv_dm_tl_intg_err	25.010s	3.164ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	25.010s	3.164ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.560s	3.843ms	2	2	100.00
		rv_dm_debug_disabled	0.860s	45.130us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.814m	94.974ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			443	461	96.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	14	77.78
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.84	95.32	80.00	89.42	74.36	85.67	98.32	56.79

Failure Buckets

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 4 failures:

Test rv_dm_stress_all has 3 failures.

7.rv_dm_stress_all.7055139838027007321923418215348961061957084601531528367680893870086416806168
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 276027703 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 276027703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.rv_dm_stress_all.103335870949734825650366861731104923986942716264237854853442455071804970107739
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 4318694453 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 4318694453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rv_dm_stress_all_with_rand_reset has 1 failures.
- 9.rv_dm_stress_all_with_rand_reset.49616272321935467449302084227349369840325662546210309884290545260998163717977
  Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 426968034 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 426968034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 3.rv_dm_stress_all_with_rand_reset.88532165764397527672522814203462435789442906783723632646840800417779467196595
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 980829811 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 980829811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.19845937784922121136094822942212639435362716087148333800154734057241797760579
    Line 271, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1888101741 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 1888101741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 2 failures:

Test rv_dm_tap_fsm_rand_reset has 2 failures.

0.rv_dm_tap_fsm_rand_reset.27411377037766853760859311715293880710734406847855507059996008560873474784753
Line 303, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 19141499060 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 19141499060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.rv_dm_tap_fsm_rand_reset.27006799538360706207214299479773913982863471109116011617794356933283194790558
Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 2772676792 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 2772676792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.4086607219399361767443910165513783241899273260865348100173558069518847170811
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1769165065 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1769165065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 26.rv_dm_stress_all.61526899539805956580401548512422445137342346377823261738083605445998903251805
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1626811030 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1626811030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.105568958087138948146630532775672968988720282156051442146431585302357708677525
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 482000757 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 482000757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 36.rv_dm_stress_all.4218312318294438468758868766629016656498945021920306631704029592177847633469
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 4098241677 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 4098241677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.61122611384173471968870189613338652010060842456731638480193085331654940440621
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @ 3771451759 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 3792685164 [0xe20fc86c])
  UVM_INFO @ 3771451759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:25) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.15713250442205503763413823923046520484157453658836737480584787534407047930091
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 693994499 ps: (rv_dm_halt_resume_whereto_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 693994499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.66731827219923806793129128485774737836763170502884798579989493689081571468791
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 363278956 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (869232552 [0x33cf6fa8] vs 3575906216 [0xd523ffa8])
  UVM_INFO @ 363278956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.56735506273561460597680451796313575909196451359352722405408764004270974502926
    Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2563951072 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (20 [0x14] vs 1375731732 [0x52000014])
  UVM_INFO @ 2563951072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.67575966899413098475597315258795082884872774632323455718147771333315749226783
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5817823019 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5817823019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```