RV_DM Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.980s	849.356us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.120s	1.004ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.710s	916.069us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.157m	49.499ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.780s	2.405ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	57.900s	19.779ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	20.140s	13.040ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.185m	66.544ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.928m	42.680ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.840s	790.903us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.190s	172.494us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	4.970s	3.073ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.850s	715.685us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.850s	510.007us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	0.980s	204.190us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.010s	143.567us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.980s	869.119us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.530s	1.159ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.170s	214.463us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.310s	610.036us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	4.970s	3.073ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.800s	312.122us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.660s	352.895us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.490s	102.009us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.163m	30.461ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.278m	4.580ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	11.070s	5.627ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.278m	4.580ms	5	5	100.00
		rv_dm_csr_rw	2.490s	102.009us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.800s	182.992us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	135.144us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.980s	849.356us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	16.810s	6.246ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.960s	286.497us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.430s	1.903ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	39.950s	15.388ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	27.840s	19.197ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	35.380s	14.772ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.733m	80.848ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	4.360s	2.835ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.810s	1.236ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.030s	284.332us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.060s	583.305us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	25.350s	9.914ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.392m	27.765ms	8	10	80.00
V2	stress_all	rv_dm_stress_all	50.230s	17.101ms	42	50	84.00
V2	alert_test	rv_dm_alert_test	1.150s	169.690us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.480s	1.067ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.480s	1.067ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.278m	4.580ms	5	5	100.00
		rv_dm_csr_hw_reset	2.660s	352.895us	5	5	100.00
		rv_dm_csr_rw	2.490s	102.009us	20	20	100.00
		rv_dm_same_csr_outstanding	8.930s	7.578ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.278m	4.580ms	5	5	100.00
		rv_dm_csr_hw_reset	2.660s	352.895us	5	5	100.00
		rv_dm_csr_rw	2.490s	102.009us	20	20	100.00
		rv_dm_same_csr_outstanding	8.930s	7.578ms	20	20	100.00
V2		TOTAL			238	248	95.97
V2S	tl_intg_err	rv_dm_sec_cm	7.660s	2.366ms	5	5	100.00
		rv_dm_tl_intg_err	25.860s	5.278ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	25.860s	5.278ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.810s	1.236ms	2	2	100.00
		rv_dm_debug_disabled	0.950s	50.376us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.856m	86.781ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			441	461	95.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	15	83.33
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.75	95.27	79.59	89.42	74.36	85.50	97.79	57.31

Failure Buckets

Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 5 failures:

Test rv_dm_stress_all has 5 failures.

22.rv_dm_stress_all.4883685851005803238154852699920932675755254451301027384782601421652755042330
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 7136408522 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 7136408522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.rv_dm_stress_all.48316965887904502132724958627010059181825061997960536414350589247127287660613
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log

      Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
  UVM_ERROR @ 1795275736 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1795275736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:31) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

0.rv_dm_stress_all_with_rand_reset.13138956254242595800867304356755827361986096770530560286580970716507366627002
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4628370746 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 4628370746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rv_dm_stress_all_with_rand_reset.23881138585477871181497613352039783271454525199188614753127328730201966830194
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1224823408 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1224823408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 2 failures.

10.rv_dm_stress_all.50059745926998666208568487122706124622061454087618012402176208675123004882799
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1803843477 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1803843477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.rv_dm_stress_all.45819691724792213009322529442634279941990133247480748850358059269492843051991
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 10946324704 ps: (rv_dm_cmderr_not_supported_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 10946324704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 3.rv_dm_stress_all_with_rand_reset.9488399205798641447902328937957362366973146244480776136492114177034352965980
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 483442463 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 483442463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rv_dm_stress_all_with_rand_reset.73239693812649955648397950010470469439777425843534340859967038324892498267019
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 926637568 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 926637568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

2.rv_dm_stress_all_with_rand_reset.63435157349044505341522536871335574907696437412958538896034824117737552934493
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 616430565 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (843990235 [0x324e44db] vs 849036507 [0x329b44db])
  UVM_INFO @ 616430565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.rv_dm_stress_all_with_rand_reset.112345788820253803847595333270396565526393470316750959186958191035274536592934
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1194644999 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2791061059 [0xa65c3643] vs 2797486147 [0xa6be4043])
  UVM_INFO @ 1194644999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 2 failures:

Test rv_dm_tap_fsm_rand_reset has 2 failures.

3.rv_dm_tap_fsm_rand_reset.94264366821851873778654326226692054804692243256694875357612036329798910912412
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 543488291 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 543488291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rv_dm_tap_fsm_rand_reset.113407059953119593157854543883143575147042157995213671493414031546631525285754
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 466180085 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1712200309 [0x660e1a75] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 466180085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:42) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.83156662285823811234013336649480572948188336277635869075826693485716172392923
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1091721255 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 1091721255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 15.rv_dm_stress_all.18805655811018683900500206702904272927097417903681406551299593536841843289320
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2800846000 ps: (rv_dm_cmderr_busy_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 2800846000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:32) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.7701951156618284890659196004136318368908175826099640542647407620822246227370
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 844110583 ps: (rv_dm_halt_resume_whereto_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 844110583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```