RV_DM Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.980s 849.356us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.120s 1.004ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.710s 916.069us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 2.157m 49.499ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 6.780s 2.405ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 57.900s 19.779ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 20.140s 13.040ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 3.185m 66.544ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.928m 42.680ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.840s 790.903us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.190s 172.494us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 4.970s 3.073ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.850s 715.685us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.850s 510.007us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.980s 204.190us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.010s 143.567us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.980s 869.119us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 2.530s 1.159ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.170s 214.463us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.310s 610.036us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 4.970s 3.073ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.800s 312.122us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.660s 352.895us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.490s 102.009us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.163m 30.461ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.278m 4.580ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 11.070s 5.627ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.278m 4.580ms 5 5 100.00
rv_dm_csr_rw 2.490s 102.009us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.800s 182.992us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.780s 135.144us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 2.980s 849.356us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 16.810s 6.246ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.960s 286.497us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.430s 1.903ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 39.950s 15.388ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 27.840s 19.197ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 35.380s 14.772ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 3.733m 80.848ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 4.360s 2.835ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.810s 1.236ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.030s 284.332us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.060s 583.305us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 25.350s 9.914ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.392m 27.765ms 8 10 80.00
V2 stress_all rv_dm_stress_all 50.230s 17.101ms 42 50 84.00
V2 alert_test rv_dm_alert_test 1.150s 169.690us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.480s 1.067ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.480s 1.067ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.278m 4.580ms 5 5 100.00
rv_dm_csr_hw_reset 2.660s 352.895us 5 5 100.00
rv_dm_csr_rw 2.490s 102.009us 20 20 100.00
rv_dm_same_csr_outstanding 8.930s 7.578ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.278m 4.580ms 5 5 100.00
rv_dm_csr_hw_reset 2.660s 352.895us 5 5 100.00
rv_dm_csr_rw 2.490s 102.009us 20 20 100.00
rv_dm_same_csr_outstanding 8.930s 7.578ms 20 20 100.00
V2 TOTAL 238 248 95.97
V2S tl_intg_err rv_dm_sec_cm 7.660s 2.366ms 5 5 100.00
rv_dm_tl_intg_err 25.860s 5.278ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 25.860s 5.278ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.810s 1.236ms 2 2 100.00
rv_dm_debug_disabled 0.950s 50.376us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.856m 86.781ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 441 461 95.66

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 15 83.33
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.75 95.27 79.59 89.42 74.36 85.50 97.79 57.31

Failure Buckets

Past Results