RV_DM Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.890s 3.913ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.000s 1.016ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.370s 1.055ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.426m 31.431ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.240s 1.056ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 25.410s 10.547ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 27.020s 14.294ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.568m 53.245ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 5.154m 104.923ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.310s 252.261us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.950s 268.522us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 4.330s 1.640ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.730s 2.236ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.590s 1.412ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 5.380s 1.747ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.120s 337.231us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.030s 590.184us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 3.320s 2.998ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.830s 155.037us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.990s 1.225ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 4.330s 1.640ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.900s 212.759us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.450s 145.084us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.570s 911.921us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 56.150s 5.738ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.184m 6.749ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.410s 5.018ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.184m 6.749ms 5 5 100.00
rv_dm_csr_rw 2.570s 911.921us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.730s 29.685us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.830s 134.432us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 3.890s 3.913ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 3.400s 969.326us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.990s 271.360us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.770s 1.048ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 15.780s 5.831ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 12.350s 4.241ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 34.710s 12.108ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.843m 37.662ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.870s 782.339us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 1.230s 462.233us 0 2 0.00
V2 ndmreset_req rv_dm_ndmreset_req 3.000s 10.011ms 1 2 50.00
V2 hart_unavail rv_dm_hart_unavail 1.300s 927.864us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 2.870s 2.304ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 2.076m 45.021ms 9 10 90.00
V2 stress_all rv_dm_stress_all 50.070s 18.845ms 35 50 70.00
V2 alert_test rv_dm_alert_test 1.040s 172.244us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.760s 1.120ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.760s 1.120ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.184m 6.749ms 5 5 100.00
rv_dm_csr_hw_reset 2.450s 145.084us 5 5 100.00
rv_dm_csr_rw 2.570s 911.921us 20 20 100.00
rv_dm_same_csr_outstanding 8.550s 7.691ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.184m 6.749ms 5 5 100.00
rv_dm_csr_hw_reset 2.450s 145.084us 5 5 100.00
rv_dm_csr_rw 2.570s 911.921us 20 20 100.00
rv_dm_same_csr_outstanding 8.550s 7.691ms 20 20 100.00
V2 TOTAL 228 248 91.94
V2S tl_intg_err rv_dm_sec_cm 5.820s 2.182ms 5 5 100.00
rv_dm_tl_intg_err 30.080s 5.726ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 30.080s 5.726ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 1.230s 462.233us 0 2 0.00
rv_dm_debug_disabled 1.050s 86.752us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 42.810s 2.797ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 431 461 93.49

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 12 66.67
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.43 95.12 79.31 89.42 74.36 85.33 98.32 55.18

Failure Buckets

Past Results