abd7ce57f2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.890s | 3.913ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 3.000s | 1.016ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 3.370s | 1.055ms | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 1.426m | 31.431ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 3.240s | 1.056ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 25.410s | 10.547ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 27.020s | 14.294ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.568m | 53.245ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 5.154m | 104.923ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.310s | 252.261us | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.950s | 268.522us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 4.330s | 1.640ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 3.730s | 2.236ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.590s | 1.412ms | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 5.380s | 1.747ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.120s | 337.231us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 2.030s | 590.184us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 3.320s | 2.998ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.830s | 155.037us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.990s | 1.225ms | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 4.330s | 1.640ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.900s | 212.759us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.450s | 145.084us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.570s | 911.921us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 56.150s | 5.738ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.184m | 6.749ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 10.410s | 5.018ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.184m | 6.749ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.570s | 911.921us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.730s | 29.685us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.830s | 134.432us | 5 | 5 | 100.00 |
| V1 | TOTAL | 176 | 176 | 100.00 | |||
| V2 | idcode | rv_dm_smoke | 3.890s | 3.913ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 3.400s | 969.326us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.990s | 271.360us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.770s | 1.048ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 15.780s | 5.831ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 12.350s | 4.241ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 34.710s | 12.108ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.843m | 37.662ms | 20 | 20 | 100.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.870s | 782.339us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 1.230s | 462.233us | 0 | 2 | 0.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 3.000s | 10.011ms | 1 | 2 | 50.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.300s | 927.864us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 2.870s | 2.304ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 2.076m | 45.021ms | 9 | 10 | 90.00 | ||
| V2 | stress_all | rv_dm_stress_all | 50.070s | 18.845ms | 35 | 50 | 70.00 |
| V2 | alert_test | rv_dm_alert_test | 1.040s | 172.244us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.760s | 1.120ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.760s | 1.120ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.184m | 6.749ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.450s | 145.084us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.570s | 911.921us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.550s | 7.691ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.184m | 6.749ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.450s | 145.084us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.570s | 911.921us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.550s | 7.691ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 228 | 248 | 91.94 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 5.820s | 2.182ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 30.080s | 5.726ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 30.080s | 5.726ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 1.230s | 462.233us | 0 | 2 | 0.00 |
| rv_dm_debug_disabled | 1.050s | 86.752us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 27 | 27 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 42.810s | 2.797ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 431 | 461 | 93.49 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 28 | 100.00 |
| V2 | 18 | 17 | 12 | 66.67 |
| V2S | 9 | 3 | 3 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 82.43 | 95.12 | 79.31 | 89.42 | 74.36 | 85.33 | 98.32 | 55.18 |
UVM_FATAL (rv_dm_base_vseq.sv:153) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 15 failures:
0.rv_dm_stress_all.9382378329876825283557182430088959619802635775988561166353244708374033196209
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 13130159182 ps: (rv_dm_base_vseq.sv:153) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
UVM_INFO @ 13130159182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all.93908917650242482907581781336856487933071301423155195827286052593084512551602
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10015711548 ps: (rv_dm_base_vseq.sv:153) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
UVM_INFO @ 10015711548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
1.rv_dm_ndmreset_req.53642145322915742277539558832230678183978186720292159302493465440136397624238
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log
UVM_FATAL @ 10010822210 ps: (rv_dm_base_vseq.sv:153) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
UVM_INFO @ 10010822210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
5.rv_dm_stress_all_with_rand_reset.20732150287146264292311505148856248431332077921807236648660834461786128434751
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4760817790 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 4760817790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.77997320544570224147503484825269574668301764982290435552753669999943353009083
Line 276, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2797069562 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 2797069562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 2 failures:
0.rv_dm_stress_all_with_rand_reset.107650012296385562791310663749686820991023891553736025705765654173488677752487
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3116230225 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3116230225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.24143362334830114834643451318405533065752791072993088539868341318805014782319
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3818716486 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3818716486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
4.rv_dm_stress_all_with_rand_reset.86832938567818523171361900149759422262108720267186758151940889400674968012367
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2165856634 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 2165856634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.50217087813957666745349944515587915473418411702893009486468737672255560792709
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2012534203 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 1 [0x1])
UVM_INFO @ 2012534203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
0.rv_dm_tap_fsm.101243041849708544957828556867613770370189854281603739092026541098272277536382
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
UVM_ERROR @ 2303838215 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 4101937115 [0xf47e97db])
UVM_INFO @ 2303838215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 1 failures:
0.rv_dm_sba_debug_disabled.10463213438204460370267986720245776867799044582168802966522881980119847501984
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
UVM_ERROR @ 357142656 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 357142656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5474) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
1.rv_dm_sba_debug_disabled.67461924704248185080174038007122947751059899056585855957924090019441567496372
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
UVM_ERROR @ 462233418 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5474) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'ha5e4b573 wdata: { [0]: 'h2c0af0f6 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 462233418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
1.rv_dm_stress_all_with_rand_reset.25273500921791642032634319739621057784959397849701632073612635479876491096953
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 589026838 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4157002981 [0xf7c6d4e5] vs 2798037222 [0xa6c6a8e6])
UVM_INFO @ 589026838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
2.rv_dm_stress_all_with_rand_reset.67154001465023521367490129899947453390324753359650273906271321221760658072033
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1863448245 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 1863448245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 1 failures:
5.rv_dm_tap_fsm_rand_reset.90939124515844648659391811995478583658556888539213644701114078608884481665693
Line 303, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10164571207 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
UVM_INFO @ 10164571207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)' has 1 failures:
5.rv_dm_stress_all.95037770876210766947786050619298018887855155127313714878406351602808492432503
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
Offending 'lc_ctrl_pkg::lc_tx_test_true_strict(lc_hw_debug_en_i)'
UVM_ERROR @ 4600017492 ps: (rv_dm_enable_checker.sv:26) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 4600017492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
8.rv_dm_stress_all_with_rand_reset.70826594837695804113363572656650085017413920625505079198903597625499421139850
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1444179868 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (20 [0x14] vs 857353684 [0x331a2dd4])
UVM_INFO @ 1444179868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---