RV_DM Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.730s 818.322us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.030s 772.194us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.280s 1.042ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 48.710s 34.839ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.140s 2.397ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 25.480s 17.316ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 19.850s 6.575ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 5.135m 129.102ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.801m 94.369ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.150s 287.243us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.950s 164.147us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.830s 907.863us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 17.430s 6.929ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.230s 1.047ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.120s 539.968us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.100s 150.157us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 6.170s 2.178ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.830s 414.727us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.470s 330.818us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 3.450s 941.262us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.830s 907.863us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.990s 178.028us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.870s 289.992us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.720s 202.576us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.266m 14.966ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.352m 16.956ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.140s 3.885ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.352m 16.956ms 5 5 100.00
rv_dm_csr_rw 2.720s 202.576us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.810s 120.477us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.920s 117.163us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 2.730s 818.322us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 3.920s 1.261ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.840s 222.701us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.620s 2.072ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 20.300s 9.292ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 32.760s 11.854ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 22.600s 16.424ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 3.094m 119.172ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.240s 533.411us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 0.770s 169.372us 0 2 0.00
V2 ndmreset_req rv_dm_ndmreset_req 14.650s 10.002ms 1 2 50.00
V2 hart_unavail rv_dm_hart_unavail 1.900s 1.063ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 18.530s 6.498ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.699m 56.031ms 8 10 80.00
V2 stress_all rv_dm_stress_all 35.790s 13.349ms 35 50 70.00
V2 alert_test rv_dm_alert_test 1.000s 133.203us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 7.040s 319.309us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 7.040s 319.309us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.352m 16.956ms 5 5 100.00
rv_dm_csr_hw_reset 2.870s 289.992us 5 5 100.00
rv_dm_csr_rw 2.720s 202.576us 20 20 100.00
rv_dm_same_csr_outstanding 8.390s 1.085ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.352m 16.956ms 5 5 100.00
rv_dm_csr_hw_reset 2.870s 289.992us 5 5 100.00
rv_dm_csr_rw 2.720s 202.576us 20 20 100.00
rv_dm_same_csr_outstanding 8.390s 1.085ms 20 20 100.00
V2 TOTAL 228 248 91.94
V2S tl_intg_err rv_dm_sec_cm 1.690s 1.639ms 5 5 100.00
rv_dm_tl_intg_err 24.360s 3.890ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 24.360s 3.890ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 0.770s 169.372us 0 2 0.00
rv_dm_debug_disabled 0.920s 52.363us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.441m 71.508ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 431 461 93.49

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 13 72.22
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.08 95.27 79.45 89.42 74.36 85.50 97.79 52.76

Failure Buckets

Past Results