RV_DM Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.730s	818.322us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.030s	772.194us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.280s	1.042ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	48.710s	34.839ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.140s	2.397ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	25.480s	17.316ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	19.850s	6.575ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	5.135m	129.102ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.801m	94.369ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.150s	287.243us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.950s	164.147us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.830s	907.863us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	17.430s	6.929ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.230s	1.047ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.120s	539.968us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.100s	150.157us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	6.170s	2.178ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.830s	414.727us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.470s	330.818us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	3.450s	941.262us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.830s	907.863us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.990s	178.028us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.870s	289.992us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.720s	202.576us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.266m	14.966ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.352m	16.956ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.140s	3.885ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.352m	16.956ms	5	5	100.00
		rv_dm_csr_rw	2.720s	202.576us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.810s	120.477us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.920s	117.163us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.730s	818.322us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.920s	1.261ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.840s	222.701us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.620s	2.072ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	20.300s	9.292ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	32.760s	11.854ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	22.600s	16.424ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.094m	119.172ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.240s	533.411us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	0.770s	169.372us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	14.650s	10.002ms	1	2	50.00
V2	hart_unavail	rv_dm_hart_unavail	1.900s	1.063ms	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	18.530s	6.498ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.699m	56.031ms	8	10	80.00
V2	stress_all	rv_dm_stress_all	35.790s	13.349ms	35	50	70.00
V2	alert_test	rv_dm_alert_test	1.000s	133.203us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.040s	319.309us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.040s	319.309us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.352m	16.956ms	5	5	100.00
		rv_dm_csr_hw_reset	2.870s	289.992us	5	5	100.00
		rv_dm_csr_rw	2.720s	202.576us	20	20	100.00
		rv_dm_same_csr_outstanding	8.390s	1.085ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.352m	16.956ms	5	5	100.00
		rv_dm_csr_hw_reset	2.870s	289.992us	5	5	100.00
		rv_dm_csr_rw	2.720s	202.576us	20	20	100.00
		rv_dm_same_csr_outstanding	8.390s	1.085ms	20	20	100.00
V2		TOTAL			228	248	91.94
V2S	tl_intg_err	rv_dm_sec_cm	1.690s	1.639ms	5	5	100.00
		rv_dm_tl_intg_err	24.360s	3.890ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.360s	3.890ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	0.770s	169.372us	0	2	0.00
		rv_dm_debug_disabled	0.920s	52.363us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.441m	71.508ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			431	461	93.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	13	72.22
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.08	95.27	79.45	89.42	74.36	85.50	97.79	52.76

Failure Buckets

UVM_FATAL (rv_dm_base_vseq.sv:149) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 16 failures:
- Test rv_dm_ndmreset_req has 1 failures.
  - 1.rv_dm_ndmreset_req.43906151310446501854407849782827319329749222356469604800186439842455780843108
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log
```
  UVM_FATAL @ 10002058889 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10002058889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 4.rv_dm_stress_all_with_rand_reset.84722898227807478909168071150744004380978979456011016001200576574909181498035
    Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15035521552 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 15035521552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rv_dm_stress_all_with_rand_reset.19075943811301371492063374134914343531389170300500176399558257855407271085444
    Line 306, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10249476072 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10249476072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 13 failures.
  - 6.rv_dm_stress_all.92861037871301542817732724341064819607636461691831397950334261979006786691734
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 15439176135 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 15439176135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all.108619623286840251799780514102312214595273546627061211072011578046691921734953
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 11506449344 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 11506449344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 2 failures:
- Test rv_dm_sba_debug_disabled has 2 failures.
  - 0.rv_dm_sba_debug_disabled.107739776154137178869706568876458746369140241162981968350193097827648854827493
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 104571917 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
  UVM_INFO @ 104571917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_sba_debug_disabled.79418091583126011454162899983918851729608043002930143964680896932784546196629
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 169371729 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
  UVM_INFO @ 169371729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 2 failures:

Test rv_dm_tap_fsm_rand_reset has 2 failures.

1.rv_dm_tap_fsm_rand_reset.108662575782168598348925876298827805432964669290572218255735585008759979474175
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 2405520875 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2716705572 [0xa1eda324] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 2405520875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_tap_fsm_rand_reset.94314769057442996942073673761065843899855754062500780856227203595976474005489
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 7885901751 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2253492495 [0x8651910f] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 7885901751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.60086453609797681100676543074563421660396117218750652762318156091772912982697
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2838002259 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 2838002259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.36370983030176270180429110169647092488359348614735845639373490771056049931596
    Line 337, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 71508489366 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 71508489366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'debug_enabled' has 2 failures:

Test rv_dm_stress_all has 2 failures.

35.rv_dm_stress_all.34514228810739354353752470381284548522566498759758714201642188527597059171752
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log

      Offending 'debug_enabled'
  UVM_ERROR @ 1875177765 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1875177765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.rv_dm_stress_all.11308714117473932833413350129171780971049462262283331034821304741750339630030
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log

      Offending 'debug_enabled'
  UVM_ERROR @ 2925890460 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 2925890460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.23363576939164746442297401088815993932899934566455184525918182505309089603021
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 894173114 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1781280314 [0x6a2c2e3a] vs 1781316668 [0x6a2cbc3c])
  UVM_INFO @ 894173114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.78565728191396152018171073311659213579416605171232984707277551097249508218794
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 314396020 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 314396020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.90106161928873509442101729551844672325288563268987995822817233499810210971056
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1799937014 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1799937014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:825) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.58594021424035998866781142007327286745519874165953083074644437205511951840193
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 707390556 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 707390556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.2987289105633618560234207283133133801462095359105137076887682819133243287775
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 194608149 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 194608149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.6769345684056968685427383559392695013777361409912501456217760688599726816929
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2765549119 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 1 [0x1])
  UVM_INFO @ 2765549119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```