RV_DM Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.140s	829.455us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.460s	322.094us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.720s	1.102ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	15.290s	5.174ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.460s	2.424ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	8.810s	4.949ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	15.340s	5.761ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.837m	43.037ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.324m	100.359ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	0.970s	389.079us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.980s	132.640us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.390s	2.128ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.560s	1.053ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	3.740s	1.208ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.050s	1.851ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.220s	389.160us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.310s	2.174ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.920s	3.083ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.920s	97.635us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	4.010s	1.200ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.390s	2.128ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.960s	139.638us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.800s	360.674us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.450s	117.951us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.132m	5.145ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.159m	14.554ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	14.070s	7.182ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.159m	14.554ms	5	5	100.00
		rv_dm_csr_rw	2.450s	117.951us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.720s	164.509us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.730s	67.239us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	3.140s	829.455us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	17.580s	6.458ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.080s	160.689us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.150s	2.173ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	40.910s	14.327ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	23.140s	7.954ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	15.980s	5.565ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.217m	49.978ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	4.920s	1.603ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	0.750s	85.489us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	14.100s	10.011ms	1	2	50.00
V2	hart_unavail	rv_dm_hart_unavail	2.490s	767.361us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.350s	9.829ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.505m	55.986ms	6	10	60.00
V2	stress_all	rv_dm_stress_all	1.016m	22.387ms	35	50	70.00
V2	alert_test	rv_dm_alert_test	1.090s	177.915us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.240s	3.641ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.240s	3.641ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.159m	14.554ms	5	5	100.00
		rv_dm_csr_hw_reset	2.800s	360.674us	5	5	100.00
		rv_dm_csr_rw	2.450s	117.951us	20	20	100.00
		rv_dm_same_csr_outstanding	7.880s	513.736us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.159m	14.554ms	5	5	100.00
		rv_dm_csr_hw_reset	2.800s	360.674us	5	5	100.00
		rv_dm_csr_rw	2.450s	117.951us	20	20	100.00
		rv_dm_same_csr_outstanding	7.880s	513.736us	20	20	100.00
V2		TOTAL			226	248	91.13
V2S	tl_intg_err	rv_dm_sec_cm	2.110s	1.836ms	5	5	100.00
		rv_dm_tl_intg_err	27.630s	5.137ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	27.630s	5.137ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	0.750s	85.489us	0	2	0.00
		rv_dm_debug_disabled	0.850s	125.323us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	45.420s	4.076ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			429	461	93.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	13	72.22
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.28	95.27	79.59	89.42	74.36	85.50	98.42	53.40

Failure Buckets

UVM_FATAL (rv_dm_base_vseq.sv:149) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 15 failures:
- Test rv_dm_ndmreset_req has 1 failures.
  - 1.rv_dm_ndmreset_req.74744859684154998840411175652750797476930194900011208217415440714130921173327
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log
```
  UVM_FATAL @ 10011148734 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10011148734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 14 failures.
  - 1.rv_dm_stress_all.65673723741108667800951081142953488875077405904279062079587948912575077923638
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 22386775917 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 22386775917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_dm_stress_all.40807424612154821078981072329984158067054303366534842112761122693237463473549
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 14724295546 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 14724295546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 4 failures:

Test rv_dm_tap_fsm_rand_reset has 4 failures.

3.rv_dm_tap_fsm_rand_reset.115147848606350003516678142570341379172980733706517415884757942044884739932980
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 6691549459 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 6691549459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_dm_tap_fsm_rand_reset.82525760951430519884971573804096160504880189545379703451184485593965107000741
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 2314619480 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 2314619480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

0.rv_dm_stress_all_with_rand_reset.14140291024224453832570674854490765658917526435433387676504074091307559797650
Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2542366170 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3852436533 [0xe59f8435] vs 3852408448 [0xe59f1680])
  UVM_INFO @ 2542366170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rv_dm_stress_all_with_rand_reset.64287450284029985734861036342655095692942627711788353534633239131893771925327
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 722618440 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (489045263 [0x1d263d0f] vs 489030572 [0x1d2603ac])
  UVM_INFO @ 722618440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 1.rv_dm_stress_all_with_rand_reset.10281587976282735199952319293693311802987679581861085026316582255025804120585
    Line 276, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4075987778 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (3 [0x3] vs 81 [0x51])
  UVM_INFO @ 4075987778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.111189704566716763768047061399791887309522633987267842274346609489611235579645
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4820614037 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (13 [0xd] vs 249 [0xf9])
  UVM_INFO @ 4820614037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 8.rv_dm_stress_all_with_rand_reset.113491820783642499541891755883687607873632854260512246390964588520373528474878
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7783110955 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 7783110955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.31164340096131938562760522222773855140545346282577774350551014975196830347732
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1249634539 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 1249634539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 0.rv_dm_sba_debug_disabled.68064457176514844671485375086293457415667704235090953133595571925950079778859
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @  85489113 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite  size: SbaAccessSize8b  addr: 'h525596cb  wdata: { [0]: 'h7cdd7eae  } readonaddr: 'hX  readondata: 'hX  autoincrement: 'h0  rdata: -  is_busy_err: 'h0  is_err: SbaErrNone  timed_out: 'h0  }
  
  UVM_INFO @  85489113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite size: SbaAccessSize16b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 1.rv_dm_sba_debug_disabled.22167182545936879702055624509860762018141436724482675739413609527622472170404
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 216625380 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite  size: SbaAccessSize16b  addr: 'hc39c7a9a  wdata: { [0]: 'h642df5f1  } readonaddr: 'hX  readondata: 'hX  autoincrement: 'h0  rdata: -  is_busy_err: 'h0  is_err: SbaErrNone  timed_out: 'h0  }
  
  UVM_INFO @ 216625380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.67835731257644181068658935956789094799868839755245834370519294787261529149581
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 700582828 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 1 [0x1])
  UVM_INFO @ 700582828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.23642236812316096590298236343672071199064899108762239688882194408896451446083
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 508775621 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (3873966592 [0xe6e80a00] vs 0 [0x0])
  UVM_INFO @ 508775621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.99989641692284269134031620580307115414327500807007576818852469251298886291645
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 453344834 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 453344834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.51028686791598562534017940752667492618577206286678149355784169290368333608166
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2024666483 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 305419896 [0x12345678]) Regname: jtag_dmi_ral.progbuf_0 reset value: 0x0
  UVM_INFO @ 2024666483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'debug_enabled' has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 18.rv_dm_stress_all.76276013827849493224289049693930919622445193964152835773716135008089692370775
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 1001764703 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1001764703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```