RV_DM Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.140s 829.455us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.460s 322.094us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.720s 1.102ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 15.290s 5.174ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.460s 2.424ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 8.810s 4.949ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 15.340s 5.761ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.837m 43.037ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 4.324m 100.359ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0.970s 389.079us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.980s 132.640us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.390s 2.128ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.560s 1.053ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 3.740s 1.208ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.050s 1.851ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.220s 389.160us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.310s 2.174ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 2.920s 3.083ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.920s 97.635us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 4.010s 1.200ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.390s 2.128ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.960s 139.638us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.800s 360.674us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.450s 117.951us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.132m 5.145ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.159m 14.554ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 14.070s 7.182ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.159m 14.554ms 5 5 100.00
rv_dm_csr_rw 2.450s 117.951us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.720s 164.509us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 67.239us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 3.140s 829.455us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 17.580s 6.458ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.080s 160.689us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.150s 2.173ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 40.910s 14.327ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 23.140s 7.954ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 15.980s 5.565ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.217m 49.978ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 4.920s 1.603ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 0.750s 85.489us 0 2 0.00
V2 ndmreset_req rv_dm_ndmreset_req 14.100s 10.011ms 1 2 50.00
V2 hart_unavail rv_dm_hart_unavail 2.490s 767.361us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 9.350s 9.829ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.505m 55.986ms 6 10 60.00
V2 stress_all rv_dm_stress_all 1.016m 22.387ms 35 50 70.00
V2 alert_test rv_dm_alert_test 1.090s 177.915us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.240s 3.641ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.240s 3.641ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.159m 14.554ms 5 5 100.00
rv_dm_csr_hw_reset 2.800s 360.674us 5 5 100.00
rv_dm_csr_rw 2.450s 117.951us 20 20 100.00
rv_dm_same_csr_outstanding 7.880s 513.736us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.159m 14.554ms 5 5 100.00
rv_dm_csr_hw_reset 2.800s 360.674us 5 5 100.00
rv_dm_csr_rw 2.450s 117.951us 20 20 100.00
rv_dm_same_csr_outstanding 7.880s 513.736us 20 20 100.00
V2 TOTAL 226 248 91.13
V2S tl_intg_err rv_dm_sec_cm 2.110s 1.836ms 5 5 100.00
rv_dm_tl_intg_err 27.630s 5.137ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 27.630s 5.137ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 0.750s 85.489us 0 2 0.00
rv_dm_debug_disabled 0.850s 125.323us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 45.420s 4.076ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 429 461 93.06

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 13 72.22
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.28 95.27 79.59 89.42 74.36 85.50 98.42 53.40

Failure Buckets

Past Results