RV_DM Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.750s	2.261ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.160s	910.597us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.540s	343.341us	19	20	95.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.150m	28.999ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.650s	377.794us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	27.230s	10.080ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	15.010s	5.062ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.437m	56.506ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.302m	221.578ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.270s	576.956us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.080s	625.605us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	5.800s	5.772ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.350s	1.025ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.530s	548.253us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.340s	238.739us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.860s	271.777us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.290s	1.655ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.540s	882.860us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.450s	318.224us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.140s	549.863us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	5.800s	5.772ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.000s	142.152us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.640s	321.440us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.730s	1.112ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.087m	5.018ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.311m	3.961ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.520s	4.463ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.311m	3.961ms	5	5	100.00
		rv_dm_csr_rw	2.730s	1.112ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.780s	97.868us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.930s	134.007us	5	5	100.00
V1		TOTAL			175	176	99.43
V2	idcode	rv_dm_smoke	6.750s	2.261ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.020s	283.117us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.600s	327.162us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.380s	2.558ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	30.360s	12.531ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	25.480s	9.186ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	20.280s	10.042ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	5.878m	126.824ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.440s	673.059us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.010s	153.657us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	7.010s	10.004ms	1	2	50.00
V2	hart_unavail	rv_dm_hart_unavail	1.280s	249.966us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	20.420s	8.496ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.554m	62.339ms	9	10	90.00
V2	stress_all	rv_dm_stress_all	57.500s	21.335ms	35	50	70.00
V2	alert_test	rv_dm_alert_test	1.140s	162.602us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.290s	248.408us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.290s	248.408us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.311m	3.961ms	5	5	100.00
		rv_dm_csr_hw_reset	2.640s	321.440us	5	5	100.00
		rv_dm_csr_rw	2.730s	1.112ms	20	20	100.00
		rv_dm_same_csr_outstanding	7.860s	720.950us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.311m	3.961ms	5	5	100.00
		rv_dm_csr_hw_reset	2.640s	321.440us	5	5	100.00
		rv_dm_csr_rw	2.730s	1.112ms	20	20	100.00
		rv_dm_same_csr_outstanding	7.860s	720.950us	20	20	100.00
V2		TOTAL			229	248	92.34
V2S	tl_intg_err	rv_dm_sec_cm	5.040s	1.523ms	5	5	100.00
		rv_dm_tl_intg_err	22.500s	8.090ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	22.500s	8.090ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.010s	153.657us	0	2	0.00
		rv_dm_debug_disabled	0.990s	72.494us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.316m	19.433ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			431	461	93.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	27	96.43
V2	18	17	13	72.22
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.53	95.32	80.00	89.42	74.36	85.67	98.42	54.56

Failure Buckets

UVM_FATAL (rv_dm_base_vseq.sv:149) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 16 failures:
- Test rv_dm_ndmreset_req has 1 failures.
  - 1.rv_dm_ndmreset_req.4493480166215183855028107179516648736331549265873538864024613205776858972225
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log
```
  UVM_FATAL @ 10004127935 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10004127935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 14 failures.
  - 1.rv_dm_stress_all.65935408823539672079070584420374479306915796525757390825111198506117775884431
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 20115082769 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 20115082769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_dm_stress_all.113450371343716635735781232476775543676152096280278904505023855926567657333553
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 12233507422 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 12233507422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.6790626093853275955892684854462213399684119707375279513935627245442043745288
    Line 273, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11031146986 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 11031146986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 2.rv_dm_stress_all_with_rand_reset.8153233985896031641929621477863805004116504176195315988185199212183286468907
    Line 303, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5225645336 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (2126788352 [0x7ec43700] vs 0 [0x0])
  UVM_INFO @ 5225645336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rv_dm_stress_all_with_rand_reset.31320654588924560066155579001472407483795466828102673673643157332903745060077
    Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1155395463 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (2399142012 [0x8f00007c] vs 0 [0x0])
  UVM_INFO @ 1155395463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

4.rv_dm_stress_all_with_rand_reset.16110761758072919235841172222527217971809687537983236686884518178373912479611
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 399518820 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1530227322 [0x5b356a7a] vs 1531931258 [0x5b4f6a7a])
  UVM_INFO @ 399518820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.rv_dm_stress_all_with_rand_reset.12478824292382754141569960222982079757983733105292174310113186311238936953215
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 235091641 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (624135121 [0x25338bd1] vs 1312008589 [0x4e33a98d])
  UVM_INFO @ 235091641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 6.rv_dm_stress_all_with_rand_reset.37696676514223386031340787963705286702065083486830053560715890534721899525692
    Line 315, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 19433344433 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 19433344433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all_with_rand_reset.6303701542879797479689645521460503236247766860693016785857528966537669308780
    Line 287, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6769494757 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 6769494757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 0.rv_dm_sba_debug_disabled.29082445079469102025526232101463014535857372078742496066241058369668531660007
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 153657078 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
  UVM_INFO @ 153657078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.87983399808717265296873157263788512005202528431169257842841243892689846967718
    Line 271, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1602079690 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1602079690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5334) { bus_op: BusOpRead size: SbaAccessSize32b addr: * wdata: - readonaddr: 'hX readondata: 'hX autoincrement: * rdata: { [*]: * } is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 1.rv_dm_sba_debug_disabled.100570747342375861969233275753488728846754331136747332559858430664406009799561
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 252628723 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5334) { bus_op: BusOpRead  size: SbaAccessSize32b  addr: 'h18ba71c  wdata: -  readonaddr: 'hX  readondata: 'hX  autoincrement: 'h0  rdata: { [0]: 'h0  } is_busy_err: 'h0  is_err: SbaErrNone  timed_out: 'h0  }
  
  UVM_INFO @ 252628723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.85290735213865705203329804020895873097956749271503333811776763022538320369370
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3528898699 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 3528898699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 2.rv_dm_tap_fsm_rand_reset.107160696410301316482891327780215381240627398092397763127915910795036020508626
    Line 359, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 34813327613 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 34813327613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.84940881792467951339702661442842926166784552030504791889342159781317260065569
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1989874929 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1989874929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_dmi_reg_frontdoor.sv:83) [ftdr] timeout occurred! has 1 failures:
- Test rv_dm_jtag_dtm_csr_rw has 1 failures.
  - 4.rv_dm_jtag_dtm_csr_rw.65402466448057639942407302516442291319305446588697542079488503727258207202793
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest/run.log
```
  UVM_FATAL @  19252341 ps: (jtag_dmi_reg_frontdoor.sv:83) [ftdr] timeout occurred!
  UVM_INFO @  19252341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'debug_enabled' has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 49.rv_dm_stress_all.57122259842886360476464990947138689605983379470997694832948085005563315194335
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 2598800729 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 2598800729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```