RV_DM Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.120s	2.513ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.890s	845.733us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.140s	1.026ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	40.120s	21.496ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.970s	1.236ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	15.010s	4.547ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	26.750s	9.176ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.604m	43.256ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.454m	75.341ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.280s	244.961us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.150s	181.245us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	15.270s	5.288ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.550s	781.791us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.680s	1.302ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.410s	1.252ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.860s	70.365us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.700s	739.151us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.990s	531.662us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.140s	496.871us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.640s	346.960us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	15.270s	5.288ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.860s	184.606us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.560s	147.933us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.530s	317.704us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.226m	14.960ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.349m	16.102ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.660s	7.543ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.349m	16.102ms	5	5	100.00
		rv_dm_csr_rw	2.530s	317.704us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.780s	177.614us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.930s	103.372us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	5.120s	2.513ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	8.440s	2.845ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.260s	283.758us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.090s	907.350us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	33.110s	13.459ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	27.470s	9.718ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	15.020s	5.887ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.289m	152.248ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	4.880s	1.506ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	0.840s	63.241us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	9.930s	10.007ms	1	2	50.00
V2	hart_unavail	rv_dm_hart_unavail	1.820s	688.501us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.700s	5.570ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	3.144m	72.890ms	9	10	90.00
V2	stress_all	rv_dm_stress_all	36.550s	13.413ms	37	50	74.00
V2	alert_test	rv_dm_alert_test	1.130s	149.166us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.710s	836.945us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.710s	836.945us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.349m	16.102ms	5	5	100.00
		rv_dm_csr_hw_reset	2.560s	147.933us	5	5	100.00
		rv_dm_csr_rw	2.530s	317.704us	20	20	100.00
		rv_dm_same_csr_outstanding	8.000s	2.246ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.349m	16.102ms	5	5	100.00
		rv_dm_csr_hw_reset	2.560s	147.933us	5	5	100.00
		rv_dm_csr_rw	2.530s	317.704us	20	20	100.00
		rv_dm_same_csr_outstanding	8.000s	2.246ms	20	20	100.00
V2		TOTAL			230	248	92.74
V2S	tl_intg_err	rv_dm_sec_cm	8.960s	2.949ms	5	5	100.00
		rv_dm_tl_intg_err	22.680s	5.541ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	22.680s	5.541ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	0.840s	63.241us	0	2	0.00
		rv_dm_debug_disabled	0.950s	48.537us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	52.100s	4.271ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			433	461	93.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	12	66.67
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.46	95.27	79.45	89.42	74.36	85.50	98.32	54.88

Failure Buckets

UVM_FATAL (rv_dm_base_vseq.sv:149) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 13 failures:
- Test rv_dm_ndmreset_req has 1 failures.
  - 1.rv_dm_ndmreset_req.100166509528313200374928470953672484247828793348269843892983274778140339281362
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log
```
  UVM_FATAL @ 10006720250 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10006720250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 11 failures.
  - 2.rv_dm_stress_all.85260924962532903936054349264888448738233497898401071496891855464833465731798
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 11043392039 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 11043392039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all.86747077103219420151196414581326050762082961917364571813026765937103974071293
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
```
  UVM_FATAL @ 15511292916 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 15511292916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.43435105901144829597421753924163220262749396085862935443691712136456476368072
    Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12089316068 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 12089316068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 0.rv_dm_stress_all_with_rand_reset.102047147216430283217270537051469125314567328409966818732573515637492972071450
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 634649329 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 634649329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.23703455426662152577937083320785307955477997742344543019898079242850036173215
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1223855623 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1223855623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 8.rv_dm_stress_all_with_rand_reset.3049428321871212874129111591919461201729088003120567625981325339454599663362
    Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4270667175 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (1 [0x1] vs 20065 [0x4e61])
  UVM_INFO @ 4270667175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.46648398536542777356726143629569199631263508716282631940964197158391208078633
    Line 282, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8867113556 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 250 [0xfa])
  UVM_INFO @ 8867113556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'debug_enabled' has 2 failures:

Test rv_dm_stress_all has 2 failures.

29.rv_dm_stress_all.16937418993400403668495856100992829003310016205855468687752426684395419807715
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log

      Offending 'debug_enabled'
  UVM_ERROR @ 468011292 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 468011292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.rv_dm_stress_all.36161788822952192867883171894841276497729574344009844423969735482492715968982
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log

      Offending 'debug_enabled'
  UVM_ERROR @ 4775903172 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 4775903172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.38936763991192032631811336351743668832563872442298620600592626445307156632659
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @ 5570090460 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 1337247257 [0x4fb4c619])
  UVM_INFO @ 5570090460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 0.rv_dm_sba_debug_disabled.87813630610381444112412583209648096587430923484265163051349823073400653377184
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @  63240512 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
  UVM_INFO @  63240512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 1.rv_dm_sba_debug_disabled.98251507177067676466764180325729803655156096037439319242989058404817984886722
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @  74126520 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5338) { bus_op: BusOpWrite  size: SbaAccessSize8b  addr: 'h42d6b208  wdata: { [0]: 'h1f8b49f  } readonaddr: 'hX  readondata: 'hX  autoincrement: 'h0  rdata: -  is_busy_err: 'h0  is_err: SbaErrNone  timed_out: 'h0  }
  
  UVM_INFO @  74126520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.77746424291405397005204716261857774092727697422199358878109323752202414946710
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 815488180 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3643807392 [0xd93016a0] vs 3643818894 [0xd930438e])
  UVM_INFO @ 815488180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.113521075429318953546431624328083986855536313558440496666588242072691701689963
    Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1148046976 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 1148046976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.33756394677941514209857754549662584796962169729859928757840337189470352431308
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 428669691 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (17 [0x11] vs 2816742729 [0xa7e41549])
  UVM_INFO @ 428669691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.50387505813581543145244434085896231704169992285538946887967022402515303596598
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 393506254 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 393506254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 6.rv_dm_tap_fsm_rand_reset.36743720356312833738977112355218024454563370766374938720711903769099549743658
    Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 17434110110 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 17434110110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:21) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.1018854416463487146022619261063110902133161539342372060100691811436612706320
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2703604048 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:21) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata2 (10 [0xa] vs 2958143569 [0xb051b051])
  UVM_INFO @ 2703604048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```