RV_DM Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.120s 2.513ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.890s 845.733us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.140s 1.026ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 40.120s 21.496ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.970s 1.236ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 15.010s 4.547ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 26.750s 9.176ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.604m 43.256ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.454m 75.341ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.280s 244.961us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.150s 181.245us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 15.270s 5.288ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.550s 781.791us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.680s 1.302ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.410s 1.252ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.860s 70.365us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.700s 739.151us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.990s 531.662us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.140s 496.871us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.640s 346.960us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 15.270s 5.288ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.860s 184.606us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.560s 147.933us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.530s 317.704us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.226m 14.960ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.349m 16.102ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.660s 7.543ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.349m 16.102ms 5 5 100.00
rv_dm_csr_rw 2.530s 317.704us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.780s 177.614us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.930s 103.372us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 5.120s 2.513ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 8.440s 2.845ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.260s 283.758us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.090s 907.350us 2 2 100.00
V2 sba rv_dm_sba_tl_access 33.110s 13.459ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 27.470s 9.718ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 15.020s 5.887ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.289m 152.248ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 4.880s 1.506ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 0.840s 63.241us 0 2 0.00
V2 ndmreset_req rv_dm_ndmreset_req 9.930s 10.007ms 1 2 50.00
V2 hart_unavail rv_dm_hart_unavail 1.820s 688.501us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 3.700s 5.570ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 3.144m 72.890ms 9 10 90.00
V2 stress_all rv_dm_stress_all 36.550s 13.413ms 37 50 74.00
V2 alert_test rv_dm_alert_test 1.130s 149.166us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.710s 836.945us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.710s 836.945us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.349m 16.102ms 5 5 100.00
rv_dm_csr_hw_reset 2.560s 147.933us 5 5 100.00
rv_dm_csr_rw 2.530s 317.704us 20 20 100.00
rv_dm_same_csr_outstanding 8.000s 2.246ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.349m 16.102ms 5 5 100.00
rv_dm_csr_hw_reset 2.560s 147.933us 5 5 100.00
rv_dm_csr_rw 2.530s 317.704us 20 20 100.00
rv_dm_same_csr_outstanding 8.000s 2.246ms 20 20 100.00
V2 TOTAL 230 248 92.74
V2S tl_intg_err rv_dm_sec_cm 8.960s 2.949ms 5 5 100.00
rv_dm_tl_intg_err 22.680s 5.541ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 22.680s 5.541ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 0.840s 63.241us 0 2 0.00
rv_dm_debug_disabled 0.950s 48.537us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 52.100s 4.271ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 433 461 93.93

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 12 66.67
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.46 95.27 79.45 89.42 74.36 85.50 98.32 54.88

Failure Buckets

Past Results