RV_DM Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.480s	3.191ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.890s	874.443us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.560s	1.092ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	45.440s	43.720ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.840s	1.722ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	51.780s	18.656ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	34.360s	12.982ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.411m	65.128ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.092m	48.390ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.720s	366.840us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.890s	475.874us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.370s	2.061ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.390s	624.012us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	3.210s	988.319us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.080s	534.170us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.850s	153.322us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.240s	383.168us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.430s	1.591ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.150s	580.111us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.280s	814.418us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.370s	2.061ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.890s	56.639us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.620s	733.702us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.580s	1.120ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.243m	7.528ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.273m	13.941ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.160s	4.319ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.273m	13.941ms	5	5	100.00
		rv_dm_csr_rw	2.580s	1.120ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.970s	129.032us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.870s	79.242us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.480s	3.191ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.900s	3.606ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.170s	808.623us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.500s	899.443us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	27.510s	9.696ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.000s	8.891ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	37.970s	15.458ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.278m	99.379ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	3.240s	1.093ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.900s	525.572us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	26.580s	10.008ms	0	2	0.00
V2	hart_unavail	rv_dm_hart_unavail	1.860s	416.388us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	22.610s	9.603ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.711m	37.501ms	6	10	60.00
V2	stress_all	rv_dm_stress_all	43.220s	15.682ms	33	50	66.00
V2	alert_test	rv_dm_alert_test	1.000s	144.833us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.910s	562.664us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.910s	562.664us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.273m	13.941ms	5	5	100.00
		rv_dm_csr_hw_reset	2.620s	733.702us	5	5	100.00
		rv_dm_csr_rw	2.580s	1.120ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.220s	1.287ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.273m	13.941ms	5	5	100.00
		rv_dm_csr_hw_reset	2.620s	733.702us	5	5	100.00
		rv_dm_csr_rw	2.580s	1.120ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.220s	1.287ms	20	20	100.00
V2		TOTAL			223	248	89.92
V2S	tl_intg_err	rv_dm_sec_cm	4.280s	1.235ms	5	5	100.00
		rv_dm_tl_intg_err	34.320s	6.637ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	34.320s	6.637ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.900s	525.572us	0	2	0.00
		rv_dm_debug_disabled	0.960s	158.449us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.101m	10.477ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			426	461	92.41

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	13	72.22
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.52	95.12	79.31	89.42	74.36	85.33	98.42	55.65

Failure Buckets

UVM_FATAL (rv_dm_base_vseq.sv:149) [rv_dm_ndmreset_req_vseq] wait timeout occurred! has 18 failures:

Test rv_dm_ndmreset_req has 2 failures.

0.rv_dm_ndmreset_req.56981298604346444154726942001994282054453115487243298031128687596780250582929
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest/run.log

  UVM_FATAL @ 10003946718 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10003946718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rv_dm_ndmreset_req.101278054349597307209986787977461712411260190277648510635212993331038123555410
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest/run.log

  UVM_FATAL @ 10008077613 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10008077613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all_with_rand_reset has 2 failures.
- 0.rv_dm_stress_all_with_rand_reset.103143602794490570088870108953466991137874427544811648176153500542100769998129
  Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10520018237 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10520018237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 6.rv_dm_stress_all_with_rand_reset.70180791182535596122675780547225415792112031638701670470667269824440656183503
  Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10477029670 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10477029670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test rv_dm_stress_all has 14 failures.

3.rv_dm_stress_all.77015374805372214562710304320663971522843381459839270714440388356799842549780
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log

  UVM_FATAL @ 13274783728 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 13274783728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rv_dm_stress_all.25302946546532664603293989705050576765571858598965934029815092462786532247704
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log

  UVM_FATAL @ 10111840027 ps: (rv_dm_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] wait timeout occurred!
  UVM_INFO @ 10111840027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 4 failures:

Test rv_dm_tap_fsm_rand_reset has 4 failures.

1.rv_dm_tap_fsm_rand_reset.55959305531704589774236193050979610089852470250420714533790626135444671243858
Line 371, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 48579999883 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 48579999883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_tap_fsm_rand_reset.39983498827679864296653377745641673525684229444674013800131368648350019497857
Line 306, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 18133308484 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 18133308484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending 'debug_enabled' has 3 failures:
- Test rv_dm_stress_all has 3 failures.
  - 24.rv_dm_stress_all.67066613795990245206289136275090685309397303105389810126223714618077397143434
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 752306295 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 752306295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 29.rv_dm_stress_all.55190396940451650329315122461209221017778076813321656208346272797900687643622
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 3368429569 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 3368429569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:327) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.77534152560743970196179884539419486882375162085660284221397156803594894459637
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  73680914 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @  73680914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rv_dm_stress_all_with_rand_reset.1274598444053657832807219990490729759009516201051604170304957230396587842717
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 153376705 ps: (rv_dm_scoreboard.sv:327) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 153376705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 0.rv_dm_sba_debug_disabled.79883169618966891147721424592349692034107179945197742299035269716046579039732
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 337400401 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
  UVM_INFO @ 337400401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:191) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5334) { bus_op: BusOpRead size: SbaAccessSize8b addr: * wdata: - readonaddr: 'hX readondata: 'hX autoincrement: * rdata: { [*]: * } is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
- Test rv_dm_sba_debug_disabled has 1 failures.
  - 1.rv_dm_sba_debug_disabled.104652723864352448975533608841305888533003988763249261689403088452646094889632
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest/run.log
```
  UVM_ERROR @ 525572399 ps: (rv_dm_scoreboard.sv:191) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5334) { bus_op: BusOpRead  size: SbaAccessSize8b  addr: 'h42f2dafe  wdata: -  readonaddr: 'hX  readondata: 'hX  autoincrement: 'h0  rdata: { [0]: 'h0  } is_busy_err: 'h0  is_err: SbaErrNone  timed_out: 'h0  }
  
  UVM_INFO @ 525572399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:23) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.22774809424093683915385788249482456718670552655151802140366587153762229837217
    Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3282566669 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3282566669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.30815086037891078236089473522439318392097520920566136099984827764109438827703
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1526305319 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1526305319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.62129038229756929882172781804711880266110244529631333296470939712860119629816
    Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1346762770 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1346762770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.10197442844748240083494851775781662603061142745284449344304775850207299674362
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4207307426 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4207307426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.92240144933330426745401238460692423138557092111504903397859831824960797798500
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 795239177 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1318516313 [0x4e96f659] vs 1314318425 [0x4e56e859])
  UVM_INFO @ 795239177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.43805246232047424249874408140659319335768278729797628318283942201768922619640
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96941109 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (17 [0x11] vs 30949 [0x78e5])
  UVM_INFO @  96941109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```