RV_DM Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.920s	3.850ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.950s	541.877us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.040s	527.165us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	53.030s	21.315ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.860s	453.388us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	44.280s	16.172ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	24.780s	9.500ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	4.666m	108.260ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.519m	133.451ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.320s	634.326us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.600s	767.658us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	7.020s	2.404ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.410s	797.015us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.940s	505.230us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.520s	510.757us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.290s	219.017us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.460s	1.387ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	3.630s	2.001ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.820s	206.757us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.110s	935.016us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	7.020s	2.404ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.140s	127.622us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.740s	232.338us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.650s	219.140us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.204m	7.328ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.296m	42.044ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	9.120s	3.365ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.296m	42.044ms	5	5	100.00
		rv_dm_csr_rw	2.650s	219.140us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.780s	135.281us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.040s	151.418us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.920s	3.850ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.020s	2.643ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.960s	549.575us	2	2	100.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.660s	698.597us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	31.550s	12.527ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.980s	14.594ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	23.930s	13.441ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.798m	43.697ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	14.860s	5.006ms	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.400s	1.876ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.250s	240.806us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.510s	307.494us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.110s	5.610ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.695m	55.472ms	5	10	50.00
V2	stress_all	rv_dm_stress_all	33.910s	11.339ms	45	50	90.00
V2	alert_test	rv_dm_alert_test	1.140s	166.933us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.990s	1.238ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.990s	1.238ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.296m	42.044ms	5	5	100.00
		rv_dm_csr_hw_reset	2.740s	232.338us	5	5	100.00
		rv_dm_csr_rw	2.650s	219.140us	20	20	100.00
		rv_dm_same_csr_outstanding	8.190s	1.115ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.296m	42.044ms	5	5	100.00
		rv_dm_csr_hw_reset	2.740s	232.338us	5	5	100.00
		rv_dm_csr_rw	2.650s	219.140us	20	20	100.00
		rv_dm_same_csr_outstanding	8.190s	1.115ms	20	20	100.00
V2		TOTAL			238	248	95.97
V2S	tl_intg_err	rv_dm_sec_cm	3.090s	791.764us	5	5	100.00
		rv_dm_tl_intg_err	26.300s	5.413ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.300s	5.413ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.400s	1.876ms	2	2	100.00
		rv_dm_debug_disabled	0.850s	45.715us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	24.100s	4.777ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			441	461	95.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	17	15	83.33
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.07	95.57	79.86	89.42	74.36	86.00	98.21	51.03

Failure Buckets

Offending 'debug_enabled' has 6 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.26499319958153574120305317332192691995053490199653208230317900426734394574448
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 901949543 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 901949543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 5 failures.
  - 8.rv_dm_stress_all.51845848239764193549621708201273449054358598911901991009820712157342674111630
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 801133460 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 801133460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 14.rv_dm_stress_all.39049040809449729876347813556163816362808675702291909310361667633547268630827
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 2048879864 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 2048879864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: * has 4 failures:

Test rv_dm_tap_fsm_rand_reset has 4 failures.

1.rv_dm_tap_fsm_rand_reset.32884661799681851959971497133344059006427926945647069591085655065919206204807
Line 363, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 45242940601 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 45242940601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rv_dm_tap_fsm_rand_reset.43372534436899261897046053537547423579914778584607227297828894521641724441092
Line 384, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @ 53919662882 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2526451350 [0x96969696] vs 1768515945 [0x69696969]) Regname: rv_dm_regs_reg_block.late_debug_enable reset value: 0x69696969
  UVM_INFO @ 53919662882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 0.rv_dm_stress_all_with_rand_reset.20944107518762099417750599507695604197243125983151403668879194661105690966897
    Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4776903693 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 4776903693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_dm_stress_all_with_rand_reset.31491767803344261427139438232444554939447938203191628469385631673850949814279
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2219356742 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 2219356742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all_with_rand_reset has 2 failures.

4.rv_dm_stress_all_with_rand_reset.49112205714311282164635556680594774106153901097748886583952245696844242206988
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1317863823 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (903966713 [0x35e16ff9] vs 903995897 [0x35e1e1f9])
  UVM_INFO @ 1317863823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_dm_stress_all_with_rand_reset.67627173845644843556983613931120760485445941953890180664713777569184284558082
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1721036843 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1252072988 [0x4aa11e1c] vs 1255869439 [0x4adb0bff])
  UVM_INFO @ 1721036843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 8.rv_dm_stress_all_with_rand_reset.45528599327865629468542455264502321399500165836735095178504346113619760770791
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1513485303 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1513485303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.102603103931516090112785419142342969417205491856422109577766903686736671633403
    Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3537747896 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3537747896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.20275892164686244173062220467433779023927574922362074280846239949764683864236
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3200290695 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (30 [0x1e] vs 2958143569 [0xb051b051])
  UVM_INFO @ 3200290695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.68859097468847756339435268484555253321494773986594544032327398614168534989020
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 610349243 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 610349243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 4.rv_dm_tap_fsm_rand_reset.70743213122735854052310792846685702618932261833894513441005989606559655157423
    Line 311, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 28245701829 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 28245701829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.44514326047332294245356389530206299785642338045417944750546337952604154470877
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 537866560 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 537866560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```