RV_DM Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.970s 1.443ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.280s 468.818us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.200s 639.726us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 22.260s 8.023ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.760s 2.294ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 34.790s 13.150ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 26.520s 13.290ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.507m 68.297ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.458m 32.722ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 4.280s 1.414ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.060s 324.704us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.490s 1.054ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.540s 1.202ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.440s 322.699us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.620s 679.386us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.980s 481.776us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.340s 1.306ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.810s 3.893ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.960s 564.576us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.000s 434.216us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.490s 1.054ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.860s 202.180us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.060s 360.031us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.500s 942.094us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.205m 15.003ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.308m 14.667ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 12.770s 5.682ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.308m 14.667ms 5 5 100.00
rv_dm_csr_rw 2.500s 942.094us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.780s 61.162us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.760s 93.361us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 4.970s 1.443ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.510s 529.858us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.250s 423.911us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.470s 783.115us 2 2 100.00
V2 sba rv_dm_sba_tl_access 23.660s 9.005ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 20.450s 7.337ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 12.450s 4.171ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.291m 26.050ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.270s 1.122ms 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 7.390s 2.411ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.050s 142.986us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.000s 112.408us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 21.920s 7.649ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.396m 49.033ms 10 10 100.00
V2 stress_all rv_dm_stress_all 30.910s 11.585ms 47 50 94.00
V2 alert_test rv_dm_alert_test 1.170s 181.452us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.500s 2.517ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.500s 2.517ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.308m 14.667ms 5 5 100.00
rv_dm_csr_hw_reset 3.060s 360.031us 5 5 100.00
rv_dm_csr_rw 2.500s 942.094us 20 20 100.00
rv_dm_same_csr_outstanding 7.960s 1.730ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.308m 14.667ms 5 5 100.00
rv_dm_csr_hw_reset 3.060s 360.031us 5 5 100.00
rv_dm_csr_rw 2.500s 942.094us 20 20 100.00
rv_dm_same_csr_outstanding 7.960s 1.730ms 20 20 100.00
V2 TOTAL 245 248 98.79
V2S tl_intg_err rv_dm_sec_cm 2.010s 659.326us 5 5 100.00
rv_dm_tl_intg_err 29.010s 5.432ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 29.010s 5.432ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 7.390s 2.411ms 2 2 100.00
rv_dm_debug_disabled 0.980s 138.351us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 54.200s 16.962ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 448 461 97.18

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 17 16 88.89
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.42 95.57 80.14 89.42 74.36 86.17 98.32 52.94

Failure Buckets

Past Results