edf2fd5092| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.020s | 1.720ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.320s | 554.944us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.930s | 881.573us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 1.023m | 21.977ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.280s | 1.210ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 14.050s | 5.245ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 41.870s | 15.111ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.624m | 52.211ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 10.137m | 233.128ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.230s | 759.438us | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.210s | 198.706us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 3.630s | 2.128ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.230s | 561.047us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.510s | 1.436ms | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 2.990s | 847.237us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.840s | 228.385us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.700s | 383.373us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 5.520s | 7.000ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 2.130s | 569.909us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.070s | 482.512us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 3.630s | 2.128ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.970s | 208.526us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.570s | 630.502us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.620s | 210.682us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.272m | 7.946ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.324m | 16.385ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 16.440s | 8.194ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.324m | 16.385ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.620s | 210.682us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.930s | 131.153us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.830s | 60.221us | 5 | 5 | 100.00 |
| V1 | TOTAL | 176 | 176 | 100.00 | |||
| V2 | idcode | rv_dm_smoke | 3.020s | 1.720ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.970s | 1.529ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.330s | 681.423us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 4.710s | 1.502ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 21.830s | 7.504ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 33.820s | 11.379ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 38.250s | 13.570ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.977m | 46.748ms | 20 | 20 | 100.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 7.140s | 2.385ms | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 2.420s | 2.188ms | 2 | 2 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.970s | 213.503us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 2.780s | 972.300us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 1.910s | 1.276ms | 0 | 1 | 0.00 |
| rv_dm_tap_fsm_rand_reset | 13.508m | 300.000ms | 7 | 10 | 70.00 | ||
| V2 | stress_all | rv_dm_stress_all | 25.440s | 10.298ms | 46 | 50 | 92.00 |
| V2 | alert_test | rv_dm_alert_test | 1.070s | 150.774us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.880s | 379.187us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.880s | 379.187us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.324m | 16.385ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.570s | 630.502us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.620s | 210.682us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.070s | 835.574us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.324m | 16.385ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.570s | 630.502us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.620s | 210.682us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.070s | 835.574us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 248 | 96.77 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.760s | 1.402ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 24.720s | 6.770ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 24.720s | 6.770ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 2.420s | 2.188ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 1.040s | 117.251us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 27 | 27 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 2.537m | 20.262ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 443 | 461 | 96.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 28 | 100.00 |
| V2 | 18 | 17 | 14 | 77.78 |
| V2S | 9 | 3 | 3 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 82.36 | 95.57 | 80.00 | 89.42 | 74.36 | 86.00 | 98.32 | 52.88 |
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 4 failures:
4.rv_dm_stress_all_with_rand_reset.60739797092524728100904061238798584414038821738617033646148278737908645643106
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20261947835 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 20261947835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all_with_rand_reset.80160106070411570076938939868617350829151468112343907503852714852546033527166
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4233948790 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 4233948790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Offending 'debug_enabled' has 4 failures:
21.rv_dm_stress_all.63653653001418487310911236676350694780718525572223807824747144326480933375728
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 4192328511 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 4192328511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all.30565645913140487384450576545360672075962701372678830459040680180880111323885
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 1441497614 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 1441497614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
2.rv_dm_stress_all_with_rand_reset.28586657171054339299757426636291736766547245251808542486923223281969824351472
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1268111852 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 1268111852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all_with_rand_reset.79183733330735027928004596071223252766917778571757160897430274464312001065140
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 173472881 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 173472881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
3.rv_dm_tap_fsm_rand_reset.83381304513851174793702950625170802157445568471173308865981504736775629207487
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_tap_fsm_rand_reset.68103575118079544085648073127766212770905188853673885036820001493367775822263
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
0.rv_dm_tap_fsm.9171048517266535898277123144138876212121901811293643128218001620704335224177
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
UVM_ERROR @ 1276235845 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 2293409686 [0x88b2a796])
UVM_INFO @ 1276235845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
0.rv_dm_stress_all_with_rand_reset.9058332904032231273448283328818970987652696068829773189654162022979914534946
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 570073501 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 570073501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
1.rv_dm_stress_all_with_rand_reset.81658779433546338532028874612736417156593584346193907180417098992043255037485
Line 293, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13545818638 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 13545818638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:379) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 1 failures:
3.rv_dm_stress_all_with_rand_reset.40054894854113657860982421782697222759420880287626620808812022955365973333122
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 730399581 ps: (rv_dm_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2271560481 [0x87654321] vs 2372243663 [0x8d6590cf]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 730399581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
5.rv_dm_tap_fsm_rand_reset.112776373408652050570942181829201699142881855785680693144463001156153104686004
Line 282, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 16529505943 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
UVM_INFO @ 16529505943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
9.rv_dm_stress_all_with_rand_reset.81575667150585564752666995409346530115031324116022342280762672691832539346808
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 524789121 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (1081449216 [0x40759b00] vs 0 [0x0])
UVM_INFO @ 524789121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---