5967df933a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 10.450s | 3.435ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.950s | 1.443ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.810s | 894.958us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 40.200s | 15.689ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.690s | 800.634us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 11.150s | 3.677ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 31.440s | 12.184ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.910m | 85.474ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 4.024m | 86.698ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.740s | 870.890us | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.930s | 172.610us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 2.120s | 509.210us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 9.140s | 3.121ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.340s | 633.426us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.830s | 1.817ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.550s | 321.767us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.250s | 1.925ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.680s | 1.149ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.080s | 542.952us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 3.300s | 1.040ms | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 2.120s | 509.210us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.920s | 164.425us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.830s | 241.294us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.730s | 406.152us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.295m | 7.413ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.309m | 13.614ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 10.960s | 7.031ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.309m | 13.614ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.730s | 406.152us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.850s | 86.057us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.830s | 65.140us | 5 | 5 | 100.00 |
| V1 | TOTAL | 176 | 176 | 100.00 | |||
| V2 | idcode | rv_dm_smoke | 10.450s | 3.435ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 2.910s | 737.384us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.980s | 377.711us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.260s | 210.708us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 3.610s | 2.395ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 39.850s | 14.468ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 34.840s | 12.786ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 20.650s | 7.358ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.039m | 24.492ms | 20 | 20 | 100.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.480s | 305.746us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 11.850s | 3.982ms | 2 | 2 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.910s | 410.340us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 2.600s | 1.335ms | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 15.740s | 5.904ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 9.385m | 300.000ms | 9 | 10 | 90.00 | ||
| V2 | stress_all | rv_dm_stress_all | 42.780s | 16.403ms | 46 | 50 | 92.00 |
| V2 | alert_test | rv_dm_alert_test | 1.130s | 156.801us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.050s | 511.188us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.050s | 511.188us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.309m | 13.614ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.830s | 241.294us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.730s | 406.152us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.470s | 835.458us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.309m | 13.614ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.830s | 241.294us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.730s | 406.152us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.470s | 835.458us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 245 | 250 | 98.00 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 6.920s | 2.248ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 29.990s | 5.365ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 29.990s | 5.365ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 11.850s | 3.982ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 1.140s | 128.936us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 27 | 27 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.377m | 13.942ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 448 | 463 | 96.76 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 28 | 100.00 |
| V2 | 18 | 18 | 16 | 88.89 |
| V2S | 9 | 3 | 3 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 82.11 | 95.67 | 80.41 | 89.75 | 73.08 | 86.17 | 98.42 | 51.29 |
Offending 'debug_enabled' has 6 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
3.rv_dm_stress_all_with_rand_reset.97737054984424355810675835432987928325485963623510487174191254770034290881486
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 207587756 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 207587756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.34249614792178216627777784941321577531314130637466946646372456528046432104274
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 1034121508 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 1034121508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 4 failures.
8.rv_dm_stress_all.39124366357412485702930906398855323688366998030619896816569875509239320114731
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 1056805313 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 1056805313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_stress_all.110786400009389010070480897435226502133241160917700087635503284387099815295258
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 2529353553 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 2529353553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
1.rv_dm_stress_all_with_rand_reset.109290687535872612582792770055850396177568488288901943905228625371962244026254
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 476883862 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 476883862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all_with_rand_reset.42688059898279392382943198609441182837846439573415798511410873667615135911345
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4654349802 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 4654349802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
0.rv_dm_stress_all_with_rand_reset.59496272602200446757429287163117790175234238557440383786775722941528846941063
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 820157144 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 820157144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.16299258973060002183792201628623624659450054109508601990921627701019320657298
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1892431203 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 1892431203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:825) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
2.rv_dm_stress_all_with_rand_reset.43657120325900080415733849901555029858493919468142807688482155142425552687123
Line 271, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2325610616 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2325610616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
3.rv_dm_tap_fsm_rand_reset.26253294167432479017215011575305746466874396700795556769106996508507838789198
Line 289, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
6.rv_dm_stress_all_with_rand_reset.86017162321910356502618675211137915560908153352037219854587993641172720779118
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2042307963 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2042307963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
9.rv_dm_stress_all_with_rand_reset.9565010711942828384524860885143956415926368479844169982655809247103356781373
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 269143283 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (735268645 [0x2bd34f25] vs 728190848 [0x2b674f80])
UVM_INFO @ 269143283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---