RV_DM Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 10.450s 3.435ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.950s 1.443ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.810s 894.958us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 40.200s 15.689ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.690s 800.634us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 11.150s 3.677ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 31.440s 12.184ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.910m 85.474ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 4.024m 86.698ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.740s 870.890us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.930s 172.610us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.120s 509.210us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 9.140s 3.121ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.340s 633.426us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.830s 1.817ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.550s 321.767us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.250s 1.925ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.680s 1.149ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.080s 542.952us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 3.300s 1.040ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.120s 509.210us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.920s 164.425us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.830s 241.294us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.730s 406.152us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.295m 7.413ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.309m 13.614ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.960s 7.031ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.309m 13.614ms 5 5 100.00
rv_dm_csr_rw 2.730s 406.152us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.850s 86.057us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.830s 65.140us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 10.450s 3.435ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.910s 737.384us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.980s 377.711us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.260s 210.708us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.610s 2.395ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 39.850s 14.468ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 34.840s 12.786ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 20.650s 7.358ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.039m 24.492ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.480s 305.746us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 11.850s 3.982ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 0.910s 410.340us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.600s 1.335ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 15.740s 5.904ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 9.385m 300.000ms 9 10 90.00
V2 stress_all rv_dm_stress_all 42.780s 16.403ms 46 50 92.00
V2 alert_test rv_dm_alert_test 1.130s 156.801us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.050s 511.188us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.050s 511.188us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.309m 13.614ms 5 5 100.00
rv_dm_csr_hw_reset 2.830s 241.294us 5 5 100.00
rv_dm_csr_rw 2.730s 406.152us 20 20 100.00
rv_dm_same_csr_outstanding 9.470s 835.458us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.309m 13.614ms 5 5 100.00
rv_dm_csr_hw_reset 2.830s 241.294us 5 5 100.00
rv_dm_csr_rw 2.730s 406.152us 20 20 100.00
rv_dm_same_csr_outstanding 9.470s 835.458us 20 20 100.00
V2 TOTAL 245 250 98.00
V2S tl_intg_err rv_dm_sec_cm 6.920s 2.248ms 5 5 100.00
rv_dm_tl_intg_err 29.990s 5.365ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 29.990s 5.365ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 11.850s 3.982ms 2 2 100.00
rv_dm_debug_disabled 1.140s 128.936us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.377m 13.942ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 448 463 96.76

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 18 16 88.89
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.11 95.67 80.41 89.75 73.08 86.17 98.42 51.29

Failure Buckets

Past Results