RV_DM Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.270s	2.778ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	4.350s	1.376ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.560s	1.067ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.037m	21.736ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.770s	714.456us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	13.640s	4.870ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	28.740s	11.043ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.189m	41.507ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.924m	103.021ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.160s	627.293us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.660s	881.063us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.290s	2.424ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.280s	1.616ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.200s	515.802us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.140s	720.703us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.930s	395.157us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.130s	1.930ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	16.640s	5.966ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.930s	555.811us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.210s	250.340us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.290s	2.424ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.860s	302.504us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.040s	314.563us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.720s	172.283us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.265m	60.969ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.326m	14.623ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.120s	4.006ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.326m	14.623ms	5	5	100.00
		rv_dm_csr_rw	2.720s	172.283us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.850s	93.681us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.740s	43.724us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	3.270s	2.778ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	4.620s	2.250ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.040s	580.242us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.970s	484.614us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.000s	451.481us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	44.310s	14.669ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	44.310s	14.674ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	30.340s	12.366ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.055m	44.316ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.360s	262.830us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.680s	736.813us	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.170s	743.533us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.750s	739.700us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	8.320s	6.605ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	11.422m	300.000ms	9	10	90.00
V2	stress_all	rv_dm_stress_all	32.310s	12.733ms	44	50	88.00
V2	alert_test	rv_dm_alert_test	1.000s	115.344us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.390s	1.547ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.390s	1.547ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.326m	14.623ms	5	5	100.00
		rv_dm_csr_hw_reset	3.040s	314.563us	5	5	100.00
		rv_dm_csr_rw	2.720s	172.283us	20	20	100.00
		rv_dm_same_csr_outstanding	8.610s	584.916us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.326m	14.623ms	5	5	100.00
		rv_dm_csr_hw_reset	3.040s	314.563us	5	5	100.00
		rv_dm_csr_rw	2.720s	172.283us	20	20	100.00
		rv_dm_same_csr_outstanding	8.610s	584.916us	20	20	100.00
V2		TOTAL			243	250	97.20
V2S	tl_intg_err	rv_dm_sec_cm	7.410s	2.346ms	5	5	100.00
		rv_dm_tl_intg_err	28.260s	5.058ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	28.260s	5.058ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.680s	736.813us	2	2	100.00
		rv_dm_debug_disabled	1.210s	99.032us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	36.300s	2.897ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			446	463	96.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	18	16	88.89
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.43	95.67	80.41	89.75	73.08	86.17	98.42	53.52

Failure Buckets

Offending 'debug_enabled' has 7 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.108604668339498669310180076240959842515970076655999052295463016550138643439186
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 258936595 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 258936595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 6 failures.
  - 9.rv_dm_stress_all.15590695875782693276050041087428749525314367249679195733008461471831060520293
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 1881567270 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1881567270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 10.rv_dm_stress_all.63023193756683421273313381873867778528110934553375316914150323533357967979045
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 5638572817 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 5638572817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 4 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 2.rv_dm_stress_all_with_rand_reset.96910323435682451940860844772746224782929604969313671698473298343949802287634
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 695017486 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (10 [0xa] vs 0 [0x0])
  UVM_INFO @ 695017486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_dm_stress_all_with_rand_reset.97543048121181730116332541360779360400797374575062694992766933607471035103195
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 264589669 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (0 [0x0] vs 15 [0xf])
  UVM_INFO @ 264589669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.73703486438543823045568647843345851551413466249441338987546687655922870831068
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 914643519 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 914643519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.76016553993071061551653383781358605395534980866842290137660321515656151407274
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5216103745 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5216103745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 2.rv_dm_tap_fsm_rand_reset.29540621110857508973334797740713619878672794062665438680541004866969013083439
    Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:23) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.101968879121658561586776843199105571331781131625542222129633609178364727768406
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1259825819 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1259825819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.111994300482464887376430658837630404482525899339898408280968026061601675740071
    Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2896852749 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (11854848 [0xb4e400] vs 0 [0x0])
  UVM_INFO @ 2896852749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.13792933505289757342803399334885420516759026997509896400794261417321755210089
    Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3027705858 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3027705858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.91989917968201927703972956614716945828869077319971315258011867620138638266109
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 259148174 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 259148174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_DM Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d51405297e`