RV_DM Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.270s 2.778ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 4.350s 1.376ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.560s 1.067ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.037m 21.736ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.770s 714.456us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 13.640s 4.870ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 28.740s 11.043ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.189m 41.507ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.924m 103.021ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.160s 627.293us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.660s 881.063us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 3.290s 2.424ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.280s 1.616ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.200s 515.802us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.140s 720.703us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.930s 395.157us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.130s 1.930ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 16.640s 5.966ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.930s 555.811us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.210s 250.340us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 3.290s 2.424ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.860s 302.504us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.040s 314.563us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.720s 172.283us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.265m 60.969ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.326m 14.623ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.120s 4.006ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.326m 14.623ms 5 5 100.00
rv_dm_csr_rw 2.720s 172.283us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.850s 93.681us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.740s 43.724us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 3.270s 2.778ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 4.620s 2.250ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.040s 580.242us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.970s 484.614us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.000s 451.481us 2 2 100.00
V2 sba rv_dm_sba_tl_access 44.310s 14.669ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 44.310s 14.674ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 30.340s 12.366ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.055m 44.316ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.360s 262.830us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 1.680s 736.813us 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.170s 743.533us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.750s 739.700us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 8.320s 6.605ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 11.422m 300.000ms 9 10 90.00
V2 stress_all rv_dm_stress_all 32.310s 12.733ms 44 50 88.00
V2 alert_test rv_dm_alert_test 1.000s 115.344us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.390s 1.547ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.390s 1.547ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.326m 14.623ms 5 5 100.00
rv_dm_csr_hw_reset 3.040s 314.563us 5 5 100.00
rv_dm_csr_rw 2.720s 172.283us 20 20 100.00
rv_dm_same_csr_outstanding 8.610s 584.916us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.326m 14.623ms 5 5 100.00
rv_dm_csr_hw_reset 3.040s 314.563us 5 5 100.00
rv_dm_csr_rw 2.720s 172.283us 20 20 100.00
rv_dm_same_csr_outstanding 8.610s 584.916us 20 20 100.00
V2 TOTAL 243 250 97.20
V2S tl_intg_err rv_dm_sec_cm 7.410s 2.346ms 5 5 100.00
rv_dm_tl_intg_err 28.260s 5.058ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 28.260s 5.058ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 1.680s 736.813us 2 2 100.00
rv_dm_debug_disabled 1.210s 99.032us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 36.300s 2.897ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 446 463 96.33

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 18 16 88.89
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.43 95.67 80.41 89.75 73.08 86.17 98.42 53.52

Failure Buckets

Past Results