c04cc5d074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 5.680s | 3.017ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.750s | 849.612us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.450s | 634.491us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 1.835m | 40.300ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.480s | 2.498ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 25.120s | 9.115ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 38.550s | 14.017ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.792m | 152.234ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.404m | 108.795ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.480s | 1.172ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.880s | 293.763us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.860s | 2.838ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.020s | 1.319ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 5.650s | 1.751ms | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.190s | 497.545us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.800s | 92.088us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 1.940s | 434.333us | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 4.670s | 2.869ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.640s | 314.284us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.320s | 235.395us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.860s | 2.838ms | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.040s | 146.800us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.630s | 184.843us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.530s | 178.173us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 53.350s | 1.532ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.340m | 8.598ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 10.950s | 4.751ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.340m | 8.598ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.530s | 178.173us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.970s | 136.433us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.730s | 36.673us | 5 | 5 | 100.00 |
| V1 | TOTAL | 176 | 176 | 100.00 | |||
| V2 | idcode | rv_dm_smoke | 5.680s | 3.017ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.730s | 1.487ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.630s | 739.732us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.910s | 378.550us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 4.510s | 1.390ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 17.480s | 14.654ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 24.110s | 8.752ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 31.080s | 11.847ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.646m | 36.557ms | 20 | 20 | 100.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.070s | 542.800us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 5.360s | 1.552ms | 2 | 2 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.970s | 556.704us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.010s | 172.269us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 14.980s | 9.337ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 2.287m | 50.635ms | 8 | 10 | 80.00 | ||
| V2 | stress_all | rv_dm_stress_all | 37.950s | 11.987ms | 44 | 50 | 88.00 |
| V2 | alert_test | rv_dm_alert_test | 1.010s | 136.189us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.140s | 260.007us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.140s | 260.007us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.340m | 8.598ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.630s | 184.843us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.530s | 178.173us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.310s | 1.411ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.340m | 8.598ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.630s | 184.843us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.530s | 178.173us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.310s | 1.411ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 242 | 250 | 96.80 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.680s | 1.521ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 25.770s | 6.453ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 25.770s | 6.453ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 5.360s | 1.552ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 0.890s | 44.274us | 2 | 2 | 100.00 | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 27 | 27 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 1.000m | 14.330ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 445 | 463 | 96.11 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 28 | 100.00 |
| V2 | 18 | 18 | 16 | 88.89 |
| V2S | 9 | 3 | 3 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 82.30 | 95.32 | 80.00 | 89.75 | 73.08 | 85.83 | 98.42 | 53.73 |
Offending 'debug_enabled' has 6 failures:
1.rv_dm_stress_all.46971675821786916148405211474945863087900517409694519574470302278838508225674
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 3085062570 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 3085062570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all.14011590845592292269634404389256621462183594121181291799952070200379451478055
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
Offending 'debug_enabled'
UVM_ERROR @ 3775191682 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
UVM_INFO @ 3775191682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 3 failures:
2.rv_dm_stress_all_with_rand_reset.79903960928593012696971870184498143283450575441133528662890219913046740913658
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 100595975 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 100595975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.38270628019465345097950817655063348077044446832837873835491712553585543098809
Line 294, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14329861420 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 14329861420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd rv_dm_mem_reg_block.flags_* (addr=*) has 2 failures:
2.rv_dm_tap_fsm_rand_reset.10902239199267250892502184272522765278799821869873805712845271242017799411642
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 21186074925 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd rv_dm_mem_reg_block.flags_115 (addr=0xdd8b95cc)
UVM_INFO @ 21186074925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_tap_fsm_rand_reset.98763309201884409664145870044385335347026929660682257513206006915750165311344
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 20163826641 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd rv_dm_mem_reg_block.flags_253 (addr=0xcc9fd7f4)
UVM_INFO @ 20163826641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:825) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.rv_dm_stress_all_with_rand_reset.26005023295380565776565963056365504610443335116640877635342649953658818854569
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1161234597 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1161234597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
1.rv_dm_stress_all_with_rand_reset.51266026417488467892766235566569823803201556351738831242234931527597161959476
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 776362794 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 776362794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
3.rv_dm_stress_all_with_rand_reset.16571339590935119988461057632030690456497908412992792421147130086155685710641
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1424528565 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
UVM_INFO @ 1424528565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:20) [rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (* [*] vs * [*]) has 1 failures:
5.rv_dm_stress_all_with_rand_reset.81600527568419058986251956281182498170063792910298474407253574988076993797041
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2475719831 ps: (rv_dm_halt_resume_whereto_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed abstractcs.busy == exp_busy (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2475719831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
6.rv_dm_stress_all_with_rand_reset.74220634721342742642131619479599726860260121072334007188263766657916595337083
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9591575683 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9591575683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
7.rv_dm_stress_all_with_rand_reset.16351185681691079990591490210393159442905640622145917442450794159811124174357
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 964295378 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (3 [0x3] vs 173 [0xad])
UVM_INFO @ 964295378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
8.rv_dm_stress_all_with_rand_reset.63127148742741744948671348058708247333164591223347773287277037190183476869355
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1372458791 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (26 [0x1a] vs 62746 [0xf51a])
UVM_INFO @ 1372458791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---