RV_DM Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.680s 3.017ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.750s 849.612us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.450s 634.491us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.835m 40.300ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.480s 2.498ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 25.120s 9.115ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 38.550s 14.017ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.792m 152.234ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.404m 108.795ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.480s 1.172ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.880s 293.763us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.860s 2.838ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.020s 1.319ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 5.650s 1.751ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.190s 497.545us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.800s 92.088us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.940s 434.333us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 4.670s 2.869ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.640s 314.284us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.320s 235.395us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.860s 2.838ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.040s 146.800us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.630s 184.843us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.530s 178.173us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 53.350s 1.532ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.340m 8.598ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 10.950s 4.751ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.340m 8.598ms 5 5 100.00
rv_dm_csr_rw 2.530s 178.173us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.970s 136.433us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 36.673us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 5.680s 3.017ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.730s 1.487ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.630s 739.732us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.910s 378.550us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 4.510s 1.390ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 17.480s 14.654ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 24.110s 8.752ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 31.080s 11.847ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.646m 36.557ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.070s 542.800us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.360s 1.552ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.970s 556.704us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.010s 172.269us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 14.980s 9.337ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.287m 50.635ms 8 10 80.00
V2 stress_all rv_dm_stress_all 37.950s 11.987ms 44 50 88.00
V2 alert_test rv_dm_alert_test 1.010s 136.189us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.140s 260.007us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.140s 260.007us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.340m 8.598ms 5 5 100.00
rv_dm_csr_hw_reset 2.630s 184.843us 5 5 100.00
rv_dm_csr_rw 2.530s 178.173us 20 20 100.00
rv_dm_same_csr_outstanding 8.310s 1.411ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.340m 8.598ms 5 5 100.00
rv_dm_csr_hw_reset 2.630s 184.843us 5 5 100.00
rv_dm_csr_rw 2.530s 178.173us 20 20 100.00
rv_dm_same_csr_outstanding 8.310s 1.411ms 20 20 100.00
V2 TOTAL 242 250 96.80
V2S tl_intg_err rv_dm_sec_cm 2.680s 1.521ms 5 5 100.00
rv_dm_tl_intg_err 25.770s 6.453ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 25.770s 6.453ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.360s 1.552ms 2 2 100.00
rv_dm_debug_disabled 0.890s 44.274us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.000m 14.330ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 445 463 96.11

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 18 18 16 88.89
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.30 95.32 80.00 89.75 73.08 85.83 98.42 53.73

Failure Buckets

Past Results