RV_DM Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.060s	1.901ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.400s	267.933us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.120s	567.459us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.779m	43.176ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.700s	1.108ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	32.470s	11.875ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	18.810s	6.849ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.711m	38.278ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.995m	99.506ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.130s	233.986us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.220s	717.387us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	5.200s	1.702ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	5.530s	3.661ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.660s	402.290us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.610s	342.944us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.870s	141.678us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.980s	824.647us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	5.910s	1.894ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.120s	334.350us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.130s	280.115us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	5.200s	1.702ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.950s	67.733us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.410s	125.980us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.660s	1.181ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.316m	30.415ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.217m	3.501ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.370s	3.424ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.217m	3.501ms	5	5	100.00
		rv_dm_csr_rw	2.660s	1.181ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.840s	143.440us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	93.085us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	3.060s	1.901ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.030s	1.345ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.210s	688.568us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.940s	112.033us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.140s	1.868ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	15.450s	6.296ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	38.500s	13.905ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	15.010s	9.682ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.074m	37.098ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.840s	729.109us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.340s	3.422ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.680s	781.313us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.810s	755.051us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	4.640s	5.008ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	3.278m	300.000ms	8	10	80.00
V2	stress_all	rv_dm_stress_all	34.720s	12.422ms	40	50	80.00
V2	alert_test	rv_dm_alert_test	1.010s	124.884us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.240s	755.075us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.240s	755.075us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.217m	3.501ms	5	5	100.00
		rv_dm_csr_hw_reset	2.410s	125.980us	5	5	100.00
		rv_dm_csr_rw	2.660s	1.181ms	20	20	100.00
		rv_dm_same_csr_outstanding	7.970s	1.140ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.217m	3.501ms	5	5	100.00
		rv_dm_csr_hw_reset	2.410s	125.980us	5	5	100.00
		rv_dm_csr_rw	2.660s	1.181ms	20	20	100.00
		rv_dm_same_csr_outstanding	7.970s	1.140ms	20	20	100.00
V2		TOTAL			237	250	94.80
V2S	tl_intg_err	rv_dm_sec_cm	2.620s	593.884us	5	5	100.00
		rv_dm_tl_intg_err	30.870s	5.763ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	30.870s	5.763ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.340s	3.422ms	2	2	100.00
		rv_dm_debug_disabled	1.070s	113.669us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	4.044m	144.735ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			440	463	95.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	18	18	15	83.33
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.58	95.42	80.97	89.91	75.00	85.83	98.00	52.94

Failure Buckets

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 5 failures:
- Test rv_dm_stress_all has 5 failures.
  - 4.rv_dm_stress_all.50268244011428598604423556847352202904113470240473260258635107817080262265790
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2130048547 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 2130048547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rv_dm_stress_all.103828536007980618237845777478766107862582220324237910762688971378529515793904
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 500369249 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 500369249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 2 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.107169625230747536376478487125710052177922528383711247583807084500795261566850
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @ 5007995396 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (0 [0x0] vs 252952255 [0xf13bebf])
  UVM_INFO @ 5007995396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 16.rv_dm_stress_all.6316769203383367920475837166586221182966018153040813736584843183182047822205
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1601655790 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (114367 [0x1bebf] vs 252952255 [0xf13bebf])
  UVM_INFO @ 1601655790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:379) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.63348370214318228464762347446302124749594285656317660548213232925805454141754
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 603236983 ps: (rv_dm_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2271560481 [0x87654321] vs 2271560502 [0x87654336]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 603236983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rv_dm_stress_all_with_rand_reset.103464356029737122068082337471840889938096750736298184502368625453397432351789
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 281376783 ps: (rv_dm_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2271560481 [0x87654321] vs 2271594948 [0x8765c9c4]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 281376783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 7.rv_dm_stress_all_with_rand_reset.27822182958177962875602454893615852470994027115976246803198722976953514808794
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 104847612 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 104847612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.101285177900356463592170786501027291326254694997944030153851207984836635205487
    Line 353, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 144735295476 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 144735295476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

21.rv_dm_stress_all.79583523857381405026745333904069893583881773800861331362788885334291884834327
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1556542709 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 1556542709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.rv_dm_stress_all.40665497359902470373757917402981850237523467753770477768079310552507712660275
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 4426162438 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 4426162438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.22985218212532536956121227743192759283075369368188232447629553173540413285625
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1585810576 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (9 [0x9] vs 931781129 [0x3789da09])
  UVM_INFO @ 1585810576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.48167468136128713831510993097420198223120541606024464666844143439839191741366
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1517933093 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1517933093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.9160908426471888049440650180000198375681870407130766467883443391083886531811
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 754852950 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1523586603 [0x5ad0162b] vs 1523586724 [0x5ad016a4])
  UVM_INFO @ 754852950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.59428492413649444151228486835606916631952328475706652655909019976242988550465
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 268073308 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 268073308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 5.rv_dm_tap_fsm_rand_reset.5917742350610431933825575057271399320240256943796677951156561227771619492065
    Line 330, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_ERROR @ 29720234235 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 29720234235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:23) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.111332399385247938472951585194877818037591065939753430732393590532865806601266
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5127452821 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5127452821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'debug_enabled' has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 8.rv_dm_stress_all.104829272068341272147750594223259637126793615008177479737592568792658948634696
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 1092695392 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 1092695392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.76248840223500155528485715440879753176007692676293333921301298792607632994702
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3936613489 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 3936613489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 9.rv_dm_tap_fsm_rand_reset.170552590519749726979747280566127732958121790624921423216044660599681420213
    Line 329, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:60) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 27.rv_dm_stress_all.15930130467288120112797697556813739294082161755852206184412233571865980218859
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 3148552710 ps: (rv_dm_ndmreset_req_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 3148552710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```