RV_DM Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.710s 3.454ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.170s 718.951us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.760s 792.471us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 48.610s 17.119ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.310s 640.329us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 18.870s 6.665ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 25.260s 15.179ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.884m 90.992ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.994m 43.004ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.900s 1.253ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.900s 240.858us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.840s 411.790us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.070s 2.705ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.330s 288.564us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.580s 651.657us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.900s 314.527us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.480s 1.075ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 3.310s 882.399us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.990s 169.474us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.890s 389.391us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.840s 411.790us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.840s 54.234us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.410s 489.406us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.540s 353.611us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 52.390s 1.453ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.377m 19.987ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 9.210s 7.374ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.377m 19.987ms 5 5 100.00
rv_dm_csr_rw 2.540s 353.611us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.920s 93.866us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.000s 142.752us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 3.710s 3.454ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 10.510s 3.941ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.520s 682.389us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.880s 85.378us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.710s 809.728us 2 2 100.00
V2 sba rv_dm_sba_tl_access 17.700s 6.429ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 37.460s 13.072ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 27.770s 9.195ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.820m 135.834ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.210s 183.112us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.040s 1.709ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.370s 517.468us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.430s 1.322ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 15.630s 9.353ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.915m 300.000ms 7 10 70.00
V2 hartsel_warl rv_dm_hartsel_warl 0.900s 187.609us 1 1 100.00
V2 stress_all rv_dm_stress_all 33.870s 12.240ms 28 50 56.00
V2 alert_test rv_dm_alert_test 1.050s 142.144us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.740s 347.174us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.740s 347.174us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.377m 19.987ms 5 5 100.00
rv_dm_csr_hw_reset 3.410s 489.406us 5 5 100.00
rv_dm_csr_rw 2.540s 353.611us 20 20 100.00
rv_dm_same_csr_outstanding 7.890s 1.811ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.377m 19.987ms 5 5 100.00
rv_dm_csr_hw_reset 3.410s 489.406us 5 5 100.00
rv_dm_csr_rw 2.540s 353.611us 20 20 100.00
rv_dm_same_csr_outstanding 7.890s 1.811ms 20 20 100.00
V2 TOTAL 226 251 90.04
V2S tl_intg_err rv_dm_sec_cm 3.790s 3.145ms 5 5 100.00
rv_dm_tl_intg_err 25.970s 7.461ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 25.970s 7.461ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.040s 1.709ms 2 2 100.00
rv_dm_debug_disabled 0.870s 49.727us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 30.890s 1.852ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 429 464 92.46

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 19 19 17 89.47
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
82.86 95.77 81.52 89.91 75.00 86.50 98.32 52.97

Failure Buckets

Past Results