RV_DM Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.870s	802.737us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.310s	1.227ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.570s	757.367us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.584m	39.195ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.420s	2.224ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	14.060s	8.136ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	30.710s	11.233ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.594m	85.739ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.591m	36.462ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.520s	541.964us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.020s	320.533us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.620s	1.178ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.600s	1.960ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.830s	462.243us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.170s	620.593us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.600s	347.881us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.050s	1.293ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	4.560s	2.973ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.160s	631.627us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.620s	664.902us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.620s	1.178ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.910s	109.254us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.590s	245.733us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.550s	210.772us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	35.920s	3.815ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.274m	4.389ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	9.970s	4.228ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.274m	4.389ms	5	5	100.00
		rv_dm_csr_rw	2.550s	210.772us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.770s	43.536us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.830s	149.117us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	1.870s	802.737us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.330s	572.084us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.220s	206.763us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.110s	368.868us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.210s	410.738us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	35.900s	13.430ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	20.090s	6.998ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	33.010s	10.826ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.482m	49.772ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.360s	784.984us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.510s	2.587ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.300s	213.068us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.120s	142.629us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.520s	5.606ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	4.465m	48.393ms	8	10	80.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.800s	295.367us	1	1	100.00
V2	stress_all	rv_dm_stress_all	32.280s	12.870ms	34	50	68.00
V2	alert_test	rv_dm_alert_test	1.080s	160.471us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.520s	655.038us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.520s	655.038us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.274m	4.389ms	5	5	100.00
		rv_dm_csr_hw_reset	2.590s	245.733us	5	5	100.00
		rv_dm_csr_rw	2.550s	210.772us	20	20	100.00
		rv_dm_same_csr_outstanding	8.380s	3.281ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.274m	4.389ms	5	5	100.00
		rv_dm_csr_hw_reset	2.590s	245.733us	5	5	100.00
		rv_dm_csr_rw	2.550s	210.772us	20	20	100.00
		rv_dm_same_csr_outstanding	8.380s	3.281ms	20	20	100.00
V2		TOTAL			233	251	92.83
V2S	tl_intg_err	rv_dm_sec_cm	5.320s	1.598ms	5	5	100.00
		rv_dm_tl_intg_err	24.250s	3.141ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.250s	3.141ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.510s	2.587ms	2	2	100.00
		rv_dm_debug_disabled	0.930s	43.818us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	4.500m	19.916ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			436	464	93.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	17	89.47
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.19	95.77	81.52	89.91	75.00	86.50	98.53	55.12

Failure Buckets

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 4 failures:
- Test rv_dm_stress_all has 4 failures.
  - 1.rv_dm_stress_all.106970051180187110913030941906124844807300233085560570604381414412063042329008
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1998051745 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1998051745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rv_dm_stress_all.25270255938854910090909793862516799580154549907307095950286475233834029111912
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 3294661341 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 3294661341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 4 failures:
- Test rv_dm_stress_all_with_rand_reset has 4 failures.
  - 1.rv_dm_stress_all_with_rand_reset.50014885434376579772247488325126459446605604869005243765946208096804314593948
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4455861121 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 4455861121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.109253296663361334120943373786468437694456795274365751687371989406829327213159
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4698119921 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 4698119921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending 'debug_enabled' has 4 failures:
- Test rv_dm_stress_all has 4 failures.
  - 3.rv_dm_stress_all.89454173346959219268661301601636319973048248448552932605281804599499413130406
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 2738323187 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 2738323187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 22.rv_dm_stress_all.110107634906979540144478837021438559676431409898021791325472633942786681939114
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
```
      Offending 'debug_enabled'
  UVM_ERROR @ 6683199823 ps: (rv_dm_enable_checker.sv:42) [ASSERT FAILED] DebugRequestNeedsDebug_A
  UVM_INFO @ 6683199823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 2 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all has 3 failures.

4.rv_dm_stress_all.105012133567022425427381369421062805083224902680812119261236028967817138843619
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1530316436 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 1530316436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.rv_dm_stress_all.113231203261399115050694250064432315848306361362818219163572763047589425266839
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2073884629 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 2073884629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (rv_dm_base_vseq.sv:180) [rv_dm_tap_fsm_vseq] wait timeout occurred! has 2 failures:
- Test rv_dm_tap_fsm_rand_reset has 2 failures.
  - 2.rv_dm_tap_fsm_rand_reset.16006840805468121525705587762484584493398875220529867458084316557464856183236
    Line 286, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 20298026388 ps: (rv_dm_base_vseq.sv:180) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq] wait timeout occurred!
  UVM_INFO @ 20298026388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rv_dm_tap_fsm_rand_reset.35355499232067928324307990770896954875178038494778870894199485685932281969781
    Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 19140604713 ps: (rv_dm_base_vseq.sv:180) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq] wait timeout occurred!
  UVM_INFO @ 19140604713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.36606600759271885575532535712741211659071156717673114097702518545448882742914
    Line 329, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 30151274002 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 30151274002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.rv_dm_stress_all_with_rand_reset.18438874630921707951895736507583545732630211851613643732495573504282746455346
    Line 282, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9769054764 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 9769054764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 7.rv_dm_stress_all_with_rand_reset.48617297985623178695563366734406221607230979559017579354732004106501154995286
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 372492240 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 372492240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.111597883746608179789324675696927948438403452378666372679284555824950803899556
    Line 376, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19915837075 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 19915837075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

12.rv_dm_stress_all.24673883584551809894643134591213485141833938721376080471793609760029231104216
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 836800048 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (3100016 [0x2f4d70] vs 456084848 [0x1b2f4d70])
  UVM_INFO @ 836800048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rv_dm_stress_all.11583389212101511252917976750650508526160703651850891927566958201162586263206
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 7060672369 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (3100016 [0x2f4d70] vs 456084848 [0x1b2f4d70])
  UVM_INFO @ 7060672369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.47029942190270304080497064353303752100097661988855368206990031450306720967704
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 908745175 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1990006533 [0x769d1705] vs 1990039980 [0x769d99ac])
  UVM_INFO @ 908745175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.98654343459528874583356959441679049914623944454102181804986168105995064935565
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1807463997 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (3584811 [0x36b32b] vs 0 [0x0])
  UVM_INFO @ 1807463997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:60) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 9.rv_dm_stress_all.74132994462705127167517407078897054637558522224971138609797859285515163172203
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1337880437 ps: (rv_dm_ndmreset_req_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 1337880437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:46) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 15.rv_dm_stress_all.97356004832187427816502223497230023830065118751345075146155985993157960112267
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1385211158 ps: (rv_dm_smoke_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1385211158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:328) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 43.rv_dm_stress_all.73049863328029833239283661609224059846274890590356254052211493596335473243387
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 858807487 ps: (rv_dm_base_vseq.sv:328) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 858807487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```