RV_DM Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.840s	714.711us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.370s	987.648us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.350s	1.010ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	22.510s	20.970ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.920s	777.533us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	9.570s	4.735ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	34.840s	13.055ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.415m	57.760ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.923m	41.495ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.680s	486.889us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.310s	179.642us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.760s	2.147ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.520s	624.573us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.990s	842.541us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.420s	272.713us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.050s	364.071us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	6.130s	2.004ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	5.440s	2.858ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.980s	90.551us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.180s	747.360us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.760s	2.147ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.870s	40.570us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.130s	346.637us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.590s	197.219us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.279m	7.682ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.302m	8.923ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	6.510s	8.117ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.302m	8.923ms	5	5	100.00
		rv_dm_csr_rw	2.590s	197.219us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.070s	166.492us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	52.816us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.840s	714.711us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.660s	1.020ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.350s	251.260us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.710s	391.549us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.200s	1.018ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	24.130s	10.265ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	47.230s	15.867ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	36.160s	12.676ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.992m	160.407ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.970s	180.391us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.460s	3.267ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.290s	164.917us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.030s	283.878us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	25.290s	8.355ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	6.012m	121.267ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.910s	248.148us	1	1	100.00
V2	stress_all	rv_dm_stress_all	26.740s	9.529ms	37	50	74.00
V2	alert_test	rv_dm_alert_test	1.030s	144.130us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.810s	608.187us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.810s	608.187us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.302m	8.923ms	5	5	100.00
		rv_dm_csr_hw_reset	3.130s	346.637us	5	5	100.00
		rv_dm_csr_rw	2.590s	197.219us	20	20	100.00
		rv_dm_same_csr_outstanding	7.970s	2.123ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.302m	8.923ms	5	5	100.00
		rv_dm_csr_hw_reset	3.130s	346.637us	5	5	100.00
		rv_dm_csr_rw	2.590s	197.219us	20	20	100.00
		rv_dm_same_csr_outstanding	7.970s	2.123ms	20	20	100.00
V2		TOTAL			238	251	94.82
V2S	tl_intg_err	rv_dm_sec_cm	2.200s	677.502us	5	5	100.00
		rv_dm_tl_intg_err	25.430s	5.409ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	25.430s	5.409ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.460s	3.267ms	2	2	100.00
		rv_dm_debug_disabled	0.960s	68.129us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.465m	40.606ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			441	464	95.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.12	95.77	81.66	89.91	75.00	86.50	97.90	55.12

Failure Buckets

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 6 failures:

Test rv_dm_stress_all has 6 failures.

20.rv_dm_stress_all.84191092505858028014787187258196435776671615228933437800660676952778583479053
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 367973428 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 367973428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.rv_dm_stress_all.106709927606215141013887854932212809851138008325276836599853262455717669134610
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 3067836662 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 3067836662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 5 failures:
- Test rv_dm_stress_all has 5 failures.
  - 2.rv_dm_stress_all.100350096620562250218890922891364211454028660540446879217108022024001504838452
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2308885728 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 2308885728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all.48553911265061304313572384341461272116807208673427816054470744034212995326170
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1062288452 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1062288452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 1.rv_dm_stress_all_with_rand_reset.84070153394932325538184785833126736692119175841588898241274854810009541347663
    Line 321, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 40606037764 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 40606037764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.104791029783202349225124777616831789300757038010561476347674918745094169831888
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5720641427 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 5720641427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:27) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 2.rv_dm_stress_all_with_rand_reset.108236934614686923755516653178911699071768078516311733420472411254744364265305
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1051179880 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1051179880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.74844615906218892372099493797471452982018837623172165082226542286638911472659
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 640168496 ps: (rv_dm_halt_resume_whereto_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 640168496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.33323825061688196446044044071386969793515355007539431461502937457670179630756
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1087300788 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1087300788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 12.rv_dm_stress_all.25268039025428122195497566698513722658931816184143683659381793685599833595761
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2583155580 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2583155580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 0.rv_dm_stress_all.7200687176994685430946528304063914196128094981272581380605995783686377935870
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 955114725 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (27308564479 [0x65bb79fff] vs 1538760703 [0x5bb79fff])
  UVM_INFO @ 955114725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.10253338431218331074228103574419740636417854231705041579172785680069959505589
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 888112208 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 888112208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.7343109294285359538700383519100888725812202010048571385592625628681218944817
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1048707835 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (16 [0x10] vs 151 [0x97])
  UVM_INFO @ 1048707835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:379) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.96754271214873341119154264866492894743801749039461504995407587818689987603206
    Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4086099242 ps: (rv_dm_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2271560481 [0x87654321] vs 1730465569 [0x6724cf21]) reg name: rv_dm_mem_reg_block.dataaddr_0
  UVM_INFO @ 4086099242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.107559267824837084989592298355972959305580168031530370506419120272666386263742
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1639494545 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (2451243008 [0x921b0000] vs 0 [0x0])
  UVM_INFO @ 1639494545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.77102506312581171860141973146905316837177203878750896661945147841407580384570
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1739728345 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1739728345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```