RV_DM Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.840s 714.711us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.370s 987.648us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.350s 1.010ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 22.510s 20.970ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.920s 777.533us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 9.570s 4.735ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 34.840s 13.055ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.415m 57.760ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.923m 41.495ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.680s 486.889us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.310s 179.642us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 3.760s 2.147ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.520s 624.573us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.990s 842.541us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.420s 272.713us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.050s 364.071us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 6.130s 2.004ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 5.440s 2.858ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.980s 90.551us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.180s 747.360us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 3.760s 2.147ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.870s 40.570us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.130s 346.637us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.590s 197.219us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.279m 7.682ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.302m 8.923ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 6.510s 8.117ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.302m 8.923ms 5 5 100.00
rv_dm_csr_rw 2.590s 197.219us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.070s 166.492us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.780s 52.816us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 2.840s 714.711us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.660s 1.020ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.350s 251.260us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.710s 391.549us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.200s 1.018ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 24.130s 10.265ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 47.230s 15.867ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 36.160s 12.676ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.992m 160.407ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.970s 180.391us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.460s 3.267ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.290s 164.917us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.030s 283.878us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 25.290s 8.355ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 6.012m 121.267ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.910s 248.148us 1 1 100.00
V2 stress_all rv_dm_stress_all 26.740s 9.529ms 37 50 74.00
V2 alert_test rv_dm_alert_test 1.030s 144.130us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.810s 608.187us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.810s 608.187us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.302m 8.923ms 5 5 100.00
rv_dm_csr_hw_reset 3.130s 346.637us 5 5 100.00
rv_dm_csr_rw 2.590s 197.219us 20 20 100.00
rv_dm_same_csr_outstanding 7.970s 2.123ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.302m 8.923ms 5 5 100.00
rv_dm_csr_hw_reset 3.130s 346.637us 5 5 100.00
rv_dm_csr_rw 2.590s 197.219us 20 20 100.00
rv_dm_same_csr_outstanding 7.970s 2.123ms 20 20 100.00
V2 TOTAL 238 251 94.82
V2S tl_intg_err rv_dm_sec_cm 2.200s 677.502us 5 5 100.00
rv_dm_tl_intg_err 25.430s 5.409ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 25.430s 5.409ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.460s 3.267ms 2 2 100.00
rv_dm_debug_disabled 0.960s 68.129us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.465m 40.606ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 441 464 95.04

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 19 19 18 94.74
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.12 95.77 81.66 89.91 75.00 86.50 97.90 55.12

Failure Buckets

Past Results