RV_DM Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	9.770s	3.491ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.770s	1.083ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.400s	641.441us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	17.740s	7.550ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.030s	1.856ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	13.990s	18.651ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	31.030s	10.144ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.719m	62.424ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.556m	51.449ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.610s	768.249us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.200s	257.058us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	11.630s	3.990ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	11.170s	3.858ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.160s	2.279ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.420s	1.785ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.090s	146.896us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.940s	590.581us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	5.930s	2.086ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.000s	310.709us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.200s	706.922us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	11.630s	3.990ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.890s	55.809us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.740s	1.291ms	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.610s	161.875us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.320m	30.469ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.348m	8.603ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.160s	3.821ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.348m	8.603ms	5	5	100.00
		rv_dm_csr_rw	2.610s	161.875us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.850s	154.919us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.850s	53.165us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	9.770s	3.491ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.540s	974.148us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.930s	436.706us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.810s	151.581us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.670s	329.320us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	22.470s	7.982ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.640s	9.050ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	31.180s	11.134ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.918m	57.657ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.150s	609.020us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.360s	4.266ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.290s	838.329us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.850s	403.889us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	2.980s	3.614ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	14.272m	81.388ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.450s	248.688us	1	1	100.00
V2	stress_all	rv_dm_stress_all	33.760s	10.966ms	36	50	72.00
V2	alert_test	rv_dm_alert_test	1.070s	151.587us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.970s	264.845us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.970s	264.845us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.348m	8.603ms	5	5	100.00
		rv_dm_csr_hw_reset	2.740s	1.291ms	5	5	100.00
		rv_dm_csr_rw	2.610s	161.875us	20	20	100.00
		rv_dm_same_csr_outstanding	11.100s	7.898ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.348m	8.603ms	5	5	100.00
		rv_dm_csr_hw_reset	2.740s	1.291ms	5	5	100.00
		rv_dm_csr_rw	2.610s	161.875us	20	20	100.00
		rv_dm_same_csr_outstanding	11.100s	7.898ms	20	20	100.00
V2		TOTAL			237	251	94.42
V2S	tl_intg_err	rv_dm_sec_cm	8.290s	2.461ms	5	5	100.00
		rv_dm_tl_intg_err	28.660s	5.914ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	28.660s	5.914ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.360s	4.266ms	2	2	100.00
		rv_dm_debug_disabled	0.900s	41.636us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.534m	49.508ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			440	464	94.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.07	95.77	81.52	89.91	76.25	86.50	98.53	53.02

Failure Buckets

UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 5 failures:
- Test rv_dm_stress_all_with_rand_reset has 5 failures.
  - 0.rv_dm_stress_all_with_rand_reset.54006201082364739638889371571122634629267008826492366188432924935797865816745
    Line 282, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 6265227838 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 6265227838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.7781746528312278214606641035836640824036578420276835019903980930042172529905
    Line 297, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13309239729 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 13309239729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 5 failures:
- Test rv_dm_stress_all has 5 failures.
  - 20.rv_dm_stress_all.113508604642088152457239172417437919318653586927216581467198991336794575242670
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 341311955 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 341311955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rv_dm_stress_all.35164167101977797971703655562070396644616406129866863211343786355455493599779
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 5182565173 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 5182565173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all has 4 failures.

6.rv_dm_stress_all.28441137724943332530162252090377107764258564102363420559285577428255539350739
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2340187811 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 2340187811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.rv_dm_stress_all.50676904246511778534355486961367032733904279010431289106240378873743985958581
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 4249549927 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 4249549927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 3.rv_dm_stress_all_with_rand_reset.32524966323291695580519695355057510349867681049750427316492144039843115216280
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1232684739 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 3439344647 [0xcd003c07])
  UVM_INFO @ 1232684739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.rv_dm_stress_all_with_rand_reset.87408145019180448225932124862963223109911545110595688033509415879589011900715
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209024201 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 3791650823 [0xe2000007])
  UVM_INFO @ 209024201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

12.rv_dm_stress_all.76740022845657367966718455892098259745682208943593682496879806954963116630139
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 4059435216 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4059435216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.rv_dm_stress_all.79494909210681392412986995082257894321828862228750705993470042989771625130267
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 9688980696 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9688980696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

38.rv_dm_stress_all.81079285699767812531139707698977290994270292448494466283254092738310725071924
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1657545517 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (3155 [0xc53] vs 592206931 [0x234c5c53])
  UVM_INFO @ 1657545517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.rv_dm_stress_all.98638422738345846688270973557369894982795514306818556940426039890169765686701
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 7831216754 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (4209 [0x1071] vs 592206931 [0x234c5c53])
  UVM_INFO @ 7831216754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.47482804497204280087824672985221552878554495301274641685067630676543905510379
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 976899629 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 976899629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.99478804500059387758265306208529936743774669260878411443139536938491026340342
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 192698732 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 192698732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.75143033580185256974904033859152581125463143313211494036678177151997330252106
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 907637640 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (10 [0xa] vs 40 [0x28])
  UVM_INFO @ 907637640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:46) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 11.rv_dm_stress_all.41501941388359208931247838577099469959761261556807313230646272573853016054211
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1954757097 ps: (rv_dm_smoke_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1954757097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```