RV_DM Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.730s 1.712ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.670s 363.130us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 4.010s 1.174ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 47.170s 18.488ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.390s 1.115ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.680s 4.176ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 39.870s 15.461ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.344m 55.932ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 9.812m 220.819ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.350s 1.026ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.430s 923.417us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.970s 1.229ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 15.580s 5.565ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.050s 911.746us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 4.090s 2.352ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.140s 331.692us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.430s 1.667ms 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 2.050s 924.258us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.020s 109.756us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.700s 427.454us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.970s 1.229ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.110s 134.797us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.870s 306.721us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.620s 1.773ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.247m 14.981ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.330m 4.514ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 7.840s 3.501ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.330m 4.514ms 5 5 100.00
rv_dm_csr_rw 2.620s 1.773ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.750s 34.459us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.990s 140.968us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 5.730s 1.712ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 9.280s 5.515ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.590s 323.639us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.990s 150.613us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.760s 1.522ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 10.950s 10.324ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 19.690s 7.183ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 50.130s 17.505ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.875m 42.854ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.210s 367.628us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 4.670s 1.456ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.750s 365.102us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.190s 205.441us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 21.500s 7.797ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.576m 58.488ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.850s 295.554us 1 1 100.00
V2 stress_all rv_dm_stress_all 35.010s 11.171ms 34 50 68.00
V2 alert_test rv_dm_alert_test 1.090s 147.642us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.680s 1.177ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.680s 1.177ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.330m 4.514ms 5 5 100.00
rv_dm_csr_hw_reset 2.870s 306.721us 5 5 100.00
rv_dm_csr_rw 2.620s 1.773ms 20 20 100.00
rv_dm_same_csr_outstanding 8.210s 1.234ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.330m 4.514ms 5 5 100.00
rv_dm_csr_hw_reset 2.870s 306.721us 5 5 100.00
rv_dm_csr_rw 2.620s 1.773ms 20 20 100.00
rv_dm_same_csr_outstanding 8.210s 1.234ms 20 20 100.00
V2 TOTAL 235 251 93.63
V2S tl_intg_err rv_dm_sec_cm 1.960s 1.194ms 5 5 100.00
rv_dm_tl_intg_err 24.890s 4.142ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 24.890s 4.142ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 4.670s 1.456ms 2 2 100.00
rv_dm_debug_disabled 0.920s 93.773us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.816m 40.161ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 438 464 94.40

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 19 19 18 94.74
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.48 95.57 81.38 89.91 77.50 86.33 98.53 55.12

Failure Buckets

Past Results