RV_DM Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.730s	1.712ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.670s	363.130us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.010s	1.174ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	47.170s	18.488ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.390s	1.115ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	12.680s	4.176ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	39.870s	15.461ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.344m	55.932ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	9.812m	220.819ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.350s	1.026ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.430s	923.417us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.970s	1.229ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	15.580s	5.565ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.050s	911.746us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	4.090s	2.352ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.140s	331.692us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.430s	1.667ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.050s	924.258us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.020s	109.756us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.700s	427.454us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.970s	1.229ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.110s	134.797us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.870s	306.721us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.620s	1.773ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.247m	14.981ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.330m	4.514ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	7.840s	3.501ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.330m	4.514ms	5	5	100.00
		rv_dm_csr_rw	2.620s	1.773ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.750s	34.459us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.990s	140.968us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	5.730s	1.712ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	9.280s	5.515ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.590s	323.639us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.990s	150.613us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.760s	1.522ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	10.950s	10.324ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	19.690s	7.183ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	50.130s	17.505ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.875m	42.854ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.210s	367.628us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.670s	1.456ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.750s	365.102us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.190s	205.441us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	21.500s	7.797ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	3.576m	58.488ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.850s	295.554us	1	1	100.00
V2	stress_all	rv_dm_stress_all	35.010s	11.171ms	34	50	68.00
V2	alert_test	rv_dm_alert_test	1.090s	147.642us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.680s	1.177ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.680s	1.177ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.330m	4.514ms	5	5	100.00
		rv_dm_csr_hw_reset	2.870s	306.721us	5	5	100.00
		rv_dm_csr_rw	2.620s	1.773ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.210s	1.234ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.330m	4.514ms	5	5	100.00
		rv_dm_csr_hw_reset	2.870s	306.721us	5	5	100.00
		rv_dm_csr_rw	2.620s	1.773ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.210s	1.234ms	20	20	100.00
V2		TOTAL			235	251	93.63
V2S	tl_intg_err	rv_dm_sec_cm	1.960s	1.194ms	5	5	100.00
		rv_dm_tl_intg_err	24.890s	4.142ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.890s	4.142ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.670s	1.456ms	2	2	100.00
		rv_dm_debug_disabled	0.920s	93.773us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.816m	40.161ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			438	464	94.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.48	95.57	81.38	89.91	77.50	86.33	98.53	55.12

Failure Buckets

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 7 failures:

Test rv_dm_stress_all has 7 failures.

2.rv_dm_stress_all.51215912586410473847915191290362123842184583030862491503073952643104272245765
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 620110095 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 620110095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.rv_dm_stress_all.98778448680634791641827369738537515633114173814419370295797761320824968495349
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 184637814 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 184637814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 6 failures:
- Test rv_dm_stress_all has 6 failures.
  - 0.rv_dm_stress_all.110811056579538068487812407226468676295174511770618472674231220660297990036911
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 4509829119 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 4509829119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rv_dm_stress_all.54414074708600295947801429214621100381304335878897832903655117673184020256042
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2520077986 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 2520077986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 6 failures:
- Test rv_dm_stress_all_with_rand_reset has 6 failures.
  - 0.rv_dm_stress_all_with_rand_reset.61431663332821267051561991446305585309572358080194561071265036462528115811255
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 817357105 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 817357105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.96260924525905999545681835728368718318165767759720248809567727346505393914784
    Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 623288949 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 623288949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

28.rv_dm_stress_all.64253149221155768082670908045115152707426715134803241071334650023514414864356
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1984982301 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1984982301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.rv_dm_stress_all.57869803616262992135842909601073863536241328800371046493809067589506336845477
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 957498825 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 957498825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.4110675478863606854378914406087375694139053081566378379837150639036817948078
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 386711526 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 386711526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:23) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.77856067203971803374762192335115869447694139266091561746508613911279713707898
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 352443113 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 352443113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.102320218427810573871646263683522742490640412121481950794205755684377063205319
    Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1900581239 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1900581239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.64031040520237710751750314887110983296366870221978531158326805622839186272894
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130918233 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (31 [0x1f] vs 245 [0xf5])
  UVM_INFO @ 130918233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:60) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 38.rv_dm_stress_all.71712346958745967720732471102356893528179377125350954552915177913133050330120
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 574048084 ps: (rv_dm_ndmreset_req_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 574048084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```