RV_DM Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.420s	2.149ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.320s	307.389us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.050s	512.567us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	42.040s	16.487ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.780s	1.618ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	10.870s	15.961ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	30.000s	12.132ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.413m	52.699ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.564m	88.961ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.120s	197.251us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.420s	497.934us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.300s	5.746ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	5.140s	2.595ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	3.480s	1.227ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.260s	1.038ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.120s	187.063us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	5.410s	1.725ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.910s	488.362us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.960s	196.527us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.460s	1.137ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.300s	5.746ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.960s	69.444us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.230s	367.625us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.640s	160.281us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.317m	33.185ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.364m	16.250ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	10.420s	4.353ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.364m	16.250ms	5	5	100.00
		rv_dm_csr_rw	2.640s	160.281us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.790s	170.303us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	77.465us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	6.420s	2.149ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	5.200s	1.586ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.080s	545.482us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.470s	520.290us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.470s	787.206us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	18.820s	6.665ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	11.480s	6.000ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	25.450s	8.890ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.772m	79.130ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.300s	410.651us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	8.090s	5.803ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.360s	819.013us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	3.190s	898.968us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	11.120s	9.408ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	6.731m	62.667ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.760s	119.015us	1	1	100.00
V2	stress_all	rv_dm_stress_all	30.300s	10.437ms	39	50	78.00
V2	alert_test	rv_dm_alert_test	0.990s	123.266us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.860s	4.513ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.860s	4.513ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.364m	16.250ms	5	5	100.00
		rv_dm_csr_hw_reset	3.230s	367.625us	5	5	100.00
		rv_dm_csr_rw	2.640s	160.281us	20	20	100.00
		rv_dm_same_csr_outstanding	8.160s	4.166ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.364m	16.250ms	5	5	100.00
		rv_dm_csr_hw_reset	3.230s	367.625us	5	5	100.00
		rv_dm_csr_rw	2.640s	160.281us	20	20	100.00
		rv_dm_same_csr_outstanding	8.160s	4.166ms	20	20	100.00
V2		TOTAL			240	251	95.62
V2S	tl_intg_err	rv_dm_sec_cm	5.120s	2.966ms	5	5	100.00
		rv_dm_tl_intg_err	32.950s	6.595ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	32.950s	6.595ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	8.090s	5.803ms	2	2	100.00
		rv_dm_debug_disabled	0.900s	120.443us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	17.470s	1.230ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			443	464	95.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.19	95.77	81.52	89.91	75.00	86.50	98.53	55.12

Failure Buckets

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 4 failures:
- Test rv_dm_stress_all has 4 failures.
  - 2.rv_dm_stress_all.50131562288683256283501634343621169335026096704793584237261392254337712762440
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 5281273572 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 5281273572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.rv_dm_stress_all.97881050219352518893963552425494000828123405553963189825206349175018775160160
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1853311325 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1853311325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all has 3 failures.

0.rv_dm_stress_all.86206885564514682370070184944169786914259998300550406550681671651484850687299
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 264497489 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (291447 [0x47277] vs 4223955575 [0xfbc47277])
  UVM_INFO @ 264497489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.rv_dm_stress_all.74849083640016281061509048705450224988862813901388408916822602682613286104808
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1728032855 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (3 [0x3] vs 4223955575 [0xfbc47277])
  UVM_INFO @ 1728032855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 3 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

3.rv_dm_stress_all_with_rand_reset.11594906119543970825865260120816754819638490612314491871462569008860417829489
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1271105725 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1271105725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 2 failures.

14.rv_dm_stress_all.88654110278180686020512726446996285257757660208612883676102957547315464428837
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 6857792141 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6857792141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.rv_dm_stress_all.81555685991806100845194794940772755946470368523669054742765483399735821054792
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 5484391113 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5484391113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

24.rv_dm_stress_all.37857979391231370016330230901052768621624494658487809154554965360323025303840
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 4669203184 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 4669203184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.rv_dm_stress_all.54108579548918579741728800513860958755107413718384296323882236208911026120037
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1189786903 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 1189786903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.10745655270035210603457669893037182097916340074549810207047165474619077967581
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 541819311 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 541819311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.54667977725551588075907518254727049457207548941751583956203427533867842686027
    Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1229734843 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 609746176 [0x2457fd00])
  UVM_INFO @ 1229734843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.44593142354992353346850842062108706982078181590367887293808224989441805762538
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 444366500 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (27 [0x1b] vs 142 [0x8e])
  UVM_INFO @ 444366500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 4.rv_dm_stress_all_with_rand_reset.112900638132198348107354958789663879860982378303592457447923910515156553590654
    Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10510024965 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 10510024965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 5.rv_dm_stress_all_with_rand_reset.48267255257500210305550889108781771233321498825109307260709744998880005069785
    Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 833747412 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 833747412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.105625922403362780381216483322022734221764645061143865003076539902135541809489
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786805381 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == as_reg.get_reset() (22 [0x16] vs 0 [0x0])
  UVM_INFO @ 786805381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_cmderr_busy_vseq.sv:38) [rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 7.rv_dm_stress_all_with_rand_reset.37517332143742748688033595479628526625299068762723098030746648865716490481686
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 709518118 ps: (rv_dm_cmderr_busy_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed abstractcs.cmderr == cmderr_exp (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 709518118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.44975611401586958718522926128686746248323152978813769854981848093924871910724
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 640428682 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (28 [0x1c] vs 205 [0xcd])
  UVM_INFO @ 640428682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.16554209667182405444033169419647232461550422996423728181369976883086210519023
    Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1030076745 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 305419896 [0x12345678]) Regname: jtag_dmi_ral.progbuf_0 reset value: 0x0
  UVM_INFO @ 1030076745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```