RV_DM Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.650s	2.585ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.120s	536.658us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.890s	449.647us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	35.860s	13.406ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.100s	1.085ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	9.440s	6.425ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	39.720s	15.330ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.575m	64.761ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	5.674m	227.100ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.250s	729.246us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.660s	684.719us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.350s	243.956us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.950s	431.616us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.290s	409.558us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.980s	3.178ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.810s	287.001us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.730s	1.810ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	8.670s	2.815ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.960s	115.482us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.900s	909.601us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.350s	243.956us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.960s	72.113us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.660s	155.876us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.410s	184.972us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.345m	29.139ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.300m	4.748ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.310s	103.858us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.300m	4.748ms	5	5	100.00
		rv_dm_csr_rw	2.410s	184.972us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.990s	130.146us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.110s	93.407us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	4.650s	2.585ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.010s	2.516ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.150s	639.919us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.760s	103.464us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.590s	298.715us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	17.300s	11.443ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	30.380s	11.359ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	20.060s	14.141ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.287m	100.034ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.860s	476.527us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	8.130s	2.777ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.830s	148.816us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.080s	722.833us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.830s	7.984ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	5.332m	33.759ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.030s	141.804us	1	1	100.00
V2	stress_all	rv_dm_stress_all	31.270s	12.541ms	29	50	58.00
V2	alert_test	rv_dm_alert_test	1.080s	164.197us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.210s	3.984ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.210s	3.984ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.300m	4.748ms	5	5	100.00
		rv_dm_csr_hw_reset	2.660s	155.876us	5	5	100.00
		rv_dm_csr_rw	2.410s	184.972us	20	20	100.00
		rv_dm_same_csr_outstanding	8.440s	2.045ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.300m	4.748ms	5	5	100.00
		rv_dm_csr_hw_reset	2.660s	155.876us	5	5	100.00
		rv_dm_csr_rw	2.410s	184.972us	20	20	100.00
		rv_dm_same_csr_outstanding	8.440s	2.045ms	20	20	100.00
V2		TOTAL			230	251	91.63
V2S	tl_intg_err	rv_dm_sec_cm	4.240s	2.524ms	5	5	100.00
		rv_dm_tl_intg_err	27.320s	7.017ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	27.320s	7.017ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	8.130s	2.777ms	2	2	100.00
		rv_dm_debug_disabled	1.050s	60.970us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.844m	8.910ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			433	464	93.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.83	95.57	81.38	89.91	75.00	86.33	98.53	53.09

Failure Buckets

UVM_FATAL (rv_dm_scoreboard.sv:335) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 10 failures:
- Test rv_dm_stress_all_with_rand_reset has 10 failures.
  - 0.rv_dm_stress_all_with_rand_reset.49059391113240828691103343251363360357461817934717320860305365741477098555748
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 413018308 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 413018308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.78236553822380119140129453839183043800291377416268655060943536783078371560755
    Line 332, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 42496568271 ps: (rv_dm_scoreboard.sv:335) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 42496568271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*])

has 9 failures:

Test rv_dm_stress_all has 9 failures.

8.rv_dm_stress_all.103194621314897704965794079565151555134222516479486085346191504093267323796537
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 240263278 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 240263278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.rv_dm_stress_all.108302629979752319732803872718041088841960461878717332276080739232624607399911
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1068265452 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 1068265452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 7 failures:
- Test rv_dm_stress_all has 7 failures.
  - 9.rv_dm_stress_all.103428729334267902014225597654711646190278167310535303955245367664097762234334
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 3683850834 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 3683850834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rv_dm_stress_all.113009982424943392300774698479083724958040699393216393568557147603937797701043
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2306225842 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 2306225842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*])

has 5 failures:

Test rv_dm_stress_all has 5 failures.

4.rv_dm_stress_all.37588890054582019729300481487281121786128154687930571888008736681437156840729
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1846554121 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (22193270 [0x152a476] vs 2236785782 [0x8552a476])
  UVM_INFO @ 1846554121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.rv_dm_stress_all.23526923160454269954847775074681364838336668666220949309843115870913912850998
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2469270724 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (54 [0x36] vs 2236785782 [0x8552a476])
  UVM_INFO @ 2469270724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.