RV_DM Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.670s	711.871us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.230s	1.036ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.980s	1.108ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	46.530s	35.204ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.810s	2.514ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	8.580s	10.362ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	25.010s	14.826ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.373m	81.525ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.016m	90.268ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.100s	539.605us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.600s	751.646us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.970s	1.132ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.460s	591.251us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.350s	759.535us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.570s	833.043us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.130s	388.002us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.040s	426.352us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.990s	867.944us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.870s	106.150us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.940s	708.640us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.970s	1.132ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.920s	38.053us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.440s	749.698us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.500s	113.626us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.188m	19.697ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.333m	7.207ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.210s	711.820us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.333m	7.207ms	5	5	100.00
		rv_dm_csr_rw	2.500s	113.626us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.960s	101.676us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.790s	46.340us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.670s	711.871us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	5.650s	2.450ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.520s	292.258us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.390s	627.013us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.500s	1.091ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	12.200s	4.453ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	28.940s	10.700ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	38.650s	14.431ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.700m	73.953ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.020s	205.872us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.620s	1.910ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.610s	386.657us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.370s	639.392us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	11.000s	6.598ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.862m	60.275ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.800s	318.279us	1	1	100.00
V2	stress_all	rv_dm_stress_all	31.880s	11.252ms	40	50	80.00
V2	alert_test	rv_dm_alert_test	1.130s	183.803us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.750s	1.266ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.750s	1.266ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.333m	7.207ms	5	5	100.00
		rv_dm_csr_hw_reset	2.440s	749.698us	5	5	100.00
		rv_dm_csr_rw	2.500s	113.626us	20	20	100.00
		rv_dm_same_csr_outstanding	8.720s	3.664ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.333m	7.207ms	5	5	100.00
		rv_dm_csr_hw_reset	2.440s	749.698us	5	5	100.00
		rv_dm_csr_rw	2.500s	113.626us	20	20	100.00
		rv_dm_same_csr_outstanding	8.720s	3.664ms	20	20	100.00
V2		TOTAL			241	251	96.02
V2S	tl_intg_err	rv_dm_sec_cm	3.080s	1.711ms	5	5	100.00
		rv_dm_tl_intg_err	30.530s	5.015ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	30.530s	5.015ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.620s	1.910ms	2	2	100.00
		rv_dm_debug_disabled	1.070s	111.660us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	13.873m	44.682ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			444	464	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.18	95.77	81.52	89.91	75.00	86.50	98.42	55.12

Failure Buckets

UVM_FATAL (rv_dm_scoreboard.sv:338) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 9 failures:
- Test rv_dm_stress_all_with_rand_reset has 9 failures.
  - 0.rv_dm_stress_all_with_rand_reset.20915100832646155685882153637449855849699601527540204286904689052800187085459
    Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5828828696 ps: (rv_dm_scoreboard.sv:338) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 5828828696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_dm_stress_all_with_rand_reset.81751090398050858814675571499822692207042247578658718690766556836693215226740
    Line 355, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 35779412839 ps: (rv_dm_scoreboard.sv:338) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 35779412839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 6 failures:

Test rv_dm_stress_all has 6 failures.

9.rv_dm_stress_all.23304558845159976222796631703825817236437907569966698911941102816470207344801
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 5251442348 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 5251442348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rv_dm_stress_all.50956189633054305189559565719252817596403443699845545247596114438989439381001
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 185103140 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 185103140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 2 failures:

Test rv_dm_stress_all has 2 failures.

16.rv_dm_stress_all.66030371836231609741225238933198972880242428593666217399992032036513440383698
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1864663368 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (80017 [0x13891] vs 184498321 [0xaff3891])
  UVM_INFO @ 1864663368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.rv_dm_stress_all.115392666290101765780700803123795764239891611698550245107584267305843349399896
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 649003007 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (536870920 [0x20000008] vs 184498321 [0xaff3891])
  UVM_INFO @ 649003007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.54365338467725069654406250399208960834553548051462817061493072722885583580874
    Line 310, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6572707259 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6572707259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 14.rv_dm_stress_all.7367599197301677468134682050372953886454262483371230473220324001730297495277
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1724452752 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1724452752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 15.rv_dm_stress_all.82149060727397543469679427950634426665658723723604293176910935712796646922374
    Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1221521999 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
  UVM_INFO @ 1221521999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```