RV_DM Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.810s	2.144ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.460s	309.424us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.540s	725.981us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	21.730s	15.168ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.670s	2.252ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	13.270s	9.114ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	18.070s	6.008ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.486m	36.633ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.821m	211.844ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.580s	657.010us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.350s	893.320us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.900s	2.154ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	10.390s	7.070ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.500s	912.203us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.440s	2.642ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.440s	313.872us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	5.340s	2.105ms	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	2.750s	887.792us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.780s	104.769us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.650s	346.059us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.900s	2.154ms	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.830s	33.147us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.760s	771.816us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.370s	544.829us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.177m	20.464ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.359m	16.672ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.820s	276.402us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.359m	16.672ms	5	5	100.00
		rv_dm_csr_rw	2.370s	544.829us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.060s	152.684us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.790s	112.169us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	2.810s	2.144ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.930s	2.142ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.900s	146.725us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.840s	528.333us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.880s	1.224ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	13.060s	4.518ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	25.500s	15.533ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	38.810s	14.437ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.118m	63.926ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.800s	161.822us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	11.800s	4.348ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.140s	217.155us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.420s	737.283us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.430s	5.622ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.794m	35.881ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.680s	99.418us	1	1	100.00
V2	stress_all	rv_dm_stress_all	32.510s	12.065ms	33	50	66.00
V2	alert_test	rv_dm_alert_test	1.070s	145.001us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.570s	556.919us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.570s	556.919us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.359m	16.672ms	5	5	100.00
		rv_dm_csr_hw_reset	2.760s	771.816us	5	5	100.00
		rv_dm_csr_rw	2.370s	544.829us	20	20	100.00
		rv_dm_same_csr_outstanding	8.760s	5.087ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.359m	16.672ms	5	5	100.00
		rv_dm_csr_hw_reset	2.760s	771.816us	5	5	100.00
		rv_dm_csr_rw	2.370s	544.829us	20	20	100.00
		rv_dm_same_csr_outstanding	8.760s	5.087ms	20	20	100.00
V2		TOTAL			234	251	93.23
V2S	tl_intg_err	rv_dm_sec_cm	3.690s	2.090ms	5	5	100.00
		rv_dm_tl_intg_err	26.470s	4.519ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.470s	4.519ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	11.800s	4.348ms	2	2	100.00
		rv_dm_debug_disabled	1.080s	123.235us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	3.028m	111.915ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			437	464	94.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.96	95.77	81.52	89.91	75.00	86.50	98.42	53.62

Failure Buckets

UVM_FATAL (rv_dm_scoreboard.sv:338) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 8 failures:
- Test rv_dm_stress_all_with_rand_reset has 8 failures.
  - 0.rv_dm_stress_all_with_rand_reset.25687976187645255476797465260475070993936814306900305672173867256769165678361
    Line 313, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 8147429040 ps: (rv_dm_scoreboard.sv:338) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 8147429040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_stress_all_with_rand_reset.10726037592279265019279056149819007347150534996374523682279502223776373526158
    Line 318, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 5482934653 ps: (rv_dm_scoreboard.sv:338) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
  UVM_INFO @ 5482934653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 8 failures:
- Test rv_dm_stress_all has 8 failures.
  - 8.rv_dm_stress_all.88006634608111871134306167587655478209421123009115412685180311251495676756713
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2342596920 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 2342596920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.rv_dm_stress_all.75824964719768695705921231748094249637870010682733398783851398099542949571696
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 699811633 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 699811633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 7 failures:

Test rv_dm_stress_all has 7 failures.

6.rv_dm_stress_all.39761199809612057439029426339326386289337097901342204296288685670559066363502
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 3295805796 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 3295805796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.rv_dm_stress_all.18300348472575886763803294413096455723928120574247959219223722652681125767565
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 840041833 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 840041833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:34) [rv_dm_ndmreset_req_vseq] Check failed val == expected_value (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 6.rv_dm_stress_all_with_rand_reset.69871287640891497095155453302649410318352013981969960120833643602456429231392
    Line 267, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1072910997 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1072910997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_stress_all has 1 failures.
  - 34.rv_dm_stress_all.12252476431008726762515858998331866777818407509223682995288898709590072653489
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2195336763 ps: (rv_dm_ndmreset_req_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed val == expected_value (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2195336763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.109612675887617666502665234017813387477112044194938320119407320868255919349681
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2187383403 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2187383403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 49.rv_dm_stress_all.91506255682164796662013140894097363742295928372554291155884067920066548014810
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 792871753 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (55 [0x37] vs 1074250295 [0x4007c237])
  UVM_INFO @ 792871753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```