RV_DM Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	13.180s	4.794ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.800s	791.814us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.650s	1.079ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	19.610s	28.665ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.910s	2.479ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	24.440s	8.626ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	36.940s	13.998ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.039m	62.893ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	7.725m	162.581ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.030s	537.944us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.960s	193.023us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.300s	769.737us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	4.030s	1.234ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.330s	439.478us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.940s	1.665ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.030s	133.396us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.100s	488.628us	2	2	100.00
V1	progbuf_busy	rv_dm_progbuf_busy	1.440s	1.006ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.970s	529.783us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.540s	338.774us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.300s	769.737us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.970s	103.308us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.800s	232.358us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.510s	202.119us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.415m	57.517ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.308m	36.309ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.810s	350.798us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.308m	36.309ms	5	5	100.00
		rv_dm_csr_rw	2.510s	202.119us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.990s	124.211us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.840s	53.682us	5	5	100.00
V1		TOTAL			176	176	100.00
V2	idcode	rv_dm_smoke	13.180s	4.794ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.310s	645.138us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.500s	599.925us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.590s	310.322us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	7.300s	2.521ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	25.390s	10.286ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	38.690s	12.817ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	31.390s	11.190ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.725m	185.193ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.190s	515.919us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.350s	2.277ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.510s	726.277us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.340s	228.232us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	8.250s	9.014ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	6.544m	53.954ms	9	10	90.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.710s	81.151us	1	1	100.00
V2	stress_all	rv_dm_stress_all	28.960s	10.829ms	35	50	70.00
V2	alert_test	rv_dm_alert_test	0.980s	131.353us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.230s	423.739us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.230s	423.739us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.308m	36.309ms	5	5	100.00
		rv_dm_csr_hw_reset	2.800s	232.358us	5	5	100.00
		rv_dm_csr_rw	2.510s	202.119us	20	20	100.00
		rv_dm_same_csr_outstanding	8.030s	587.716us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.308m	36.309ms	5	5	100.00
		rv_dm_csr_hw_reset	2.800s	232.358us	5	5	100.00
		rv_dm_csr_rw	2.510s	202.119us	20	20	100.00
		rv_dm_same_csr_outstanding	8.030s	587.716us	20	20	100.00
V2		TOTAL			235	251	93.63
V2S	tl_intg_err	rv_dm_sec_cm	7.700s	2.811ms	5	5	100.00
		rv_dm_tl_intg_err	26.860s	4.224ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.860s	4.224ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.350s	2.277ms	2	2	100.00
		rv_dm_debug_disabled	1.010s	128.910us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	19.767m	209.525ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			444	464	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	28	28	28	100.00
V2	19	19	17	89.47
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.52	95.82	84.14	89.91	75.00	88.33	98.53	52.90

Failure Buckets

UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 11 failures:

Test rv_dm_stress_all has 11 failures.

10.rv_dm_stress_all.80239864219307215345700350456872118300166073294507181551175203077977999658523
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2737638383 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 2737638383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.rv_dm_stress_all.90372091588166837301620046025628864002397167754146036534845953060632153286214
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 564116668 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 564116668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*]) has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 7.rv_dm_stress_all_with_rand_reset.20838218831103679100116947393674773450129758795309171550017719360394800124266
    Line 484, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18855673750 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18855673750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.40586854405655407571963287520234665936137883405606387358359709193859514453820
    Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 846144722 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 846144722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:87) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req) has 2 failures:
- Test rv_dm_stress_all has 2 failures.
  - 11.rv_dm_stress_all.18881474799681800513720535046831404718022731609750151726118637352445671474967
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2218752428 ps: (rv_dm_ndmreset_req_vseq.sv:87) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 2218752428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.rv_dm_stress_all.105390467120519882194979570859529451562355430662671280988358960247094984850482
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 10829215661 ps: (rv_dm_ndmreset_req_vseq.sv:87) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 10829215661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.75470784753176896214153624829873738070355092446590138628669281144262200883340
    Line 402, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18371954916 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (9 [0x9] vs 18446744073709551615 [0xffffffffffffffff])
  UVM_INFO @ 18371954916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 3.rv_dm_stress_all_with_rand_reset.78916960399261784051441354109160270341569026321111562259105330668640433267788
    Line 291, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5899154303 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5899154303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 7.rv_dm_tap_fsm_rand_reset.53707677005987833659672141559289890771130589051625515849806868510882657669230
    Line 323, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 34461056081 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 34461056081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 13.rv_dm_stress_all.35930581999152888100388791970374257807804396093438863356967407787005699543945
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 5475405494 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (5222 [0x1466] vs 185234534 [0xb0a7466])
  UVM_INFO @ 5475405494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 38.rv_dm_stress_all.60574907587676557992817113084243586168843281670438490324515319972068686255253
    Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1993047180 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 1993047180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```