RV_DM Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 13.180s 4.794ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.800s 791.814us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.650s 1.079ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 19.610s 28.665ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 6.910s 2.479ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 24.440s 8.626ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 36.940s 13.998ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.039m 62.893ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 7.725m 162.581ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.030s 537.944us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.960s 193.023us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.300s 769.737us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 4.030s 1.234ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.330s 439.478us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.940s 1.665ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.030s 133.396us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.100s 488.628us 2 2 100.00
V1 progbuf_busy rv_dm_progbuf_busy 1.440s 1.006ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.970s 529.783us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.540s 338.774us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.300s 769.737us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.970s 103.308us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.800s 232.358us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.510s 202.119us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.415m 57.517ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.308m 36.309ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.810s 350.798us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.308m 36.309ms 5 5 100.00
rv_dm_csr_rw 2.510s 202.119us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.990s 124.211us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.840s 53.682us 5 5 100.00
V1 TOTAL 176 176 100.00
V2 idcode rv_dm_smoke 13.180s 4.794ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.310s 645.138us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.500s 599.925us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.590s 310.322us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 7.300s 2.521ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 25.390s 10.286ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 38.690s 12.817ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 31.390s 11.190ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.725m 185.193ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.190s 515.919us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 6.350s 2.277ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.510s 726.277us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.340s 228.232us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 8.250s 9.014ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 6.544m 53.954ms 9 10 90.00
V2 hartsel_warl rv_dm_hartsel_warl 0.710s 81.151us 1 1 100.00
V2 stress_all rv_dm_stress_all 28.960s 10.829ms 35 50 70.00
V2 alert_test rv_dm_alert_test 0.980s 131.353us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.230s 423.739us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.230s 423.739us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.308m 36.309ms 5 5 100.00
rv_dm_csr_hw_reset 2.800s 232.358us 5 5 100.00
rv_dm_csr_rw 2.510s 202.119us 20 20 100.00
rv_dm_same_csr_outstanding 8.030s 587.716us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.308m 36.309ms 5 5 100.00
rv_dm_csr_hw_reset 2.800s 232.358us 5 5 100.00
rv_dm_csr_rw 2.510s 202.119us 20 20 100.00
rv_dm_same_csr_outstanding 8.030s 587.716us 20 20 100.00
V2 TOTAL 235 251 93.63
V2S tl_intg_err rv_dm_sec_cm 7.700s 2.811ms 5 5 100.00
rv_dm_tl_intg_err 26.860s 4.224ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 26.860s 4.224ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 6.350s 2.277ms 2 2 100.00
rv_dm_debug_disabled 1.010s 128.910us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 19.767m 209.525ms 6 10 60.00
V3 TOTAL 6 10 60.00
TOTAL 444 464 95.69

Testplan Progress

Items Total Written Passing Progress
V1 28 28 28 100.00
V2 19 19 17 89.47
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.52 95.82 84.14 89.91 75.00 88.33 98.53 52.90

Failure Buckets

Past Results