RV_DM Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.480s	2.604ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.470s	1.114ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.030s	465.010us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.381m	27.616ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.460s	1.893ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	16.570s	6.642ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	40.660s	14.802ms	19	20	95.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.783m	86.608ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.399m	60.751ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.360s	277.295us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.020s	514.702us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.290s	821.231us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	4.060s	4.188ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.170s	1.049ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.020s	1.744ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.180s	267.530us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.030s	459.864us	2	2	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.360s	277.295us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.080s	146.277us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.290s	549.502us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.290s	821.231us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.910s	131.729us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.860s	373.609us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.590s	222.247us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.161m	20.404ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.329m	16.691ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.960s	499.215us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.329m	16.691ms	5	5	100.00
		rv_dm_csr_rw	2.590s	222.247us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.890s	100.265us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.830s	167.974us	5	5	100.00
V1		TOTAL			173	174	99.43
V2	idcode	rv_dm_smoke	4.480s	2.604ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	6.490s	4.662ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.000s	93.566us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.030s	553.455us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.280s	481.597us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	31.310s	11.318ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	32.710s	10.774ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	29.350s	10.745ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.669m	87.268ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.860s	162.664us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	8.260s	2.968ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.640s	701.795us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.220s	210.318us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	3.520s	6.033ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	13.016m	140.989ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.760s	53.375us	1	1	100.00
V2	stress_all	rv_dm_stress_all	17.610s	9.705ms	34	50	68.00
V2	alert_test	rv_dm_alert_test	1.160s	173.945us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.470s	450.598us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.470s	450.598us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.329m	16.691ms	5	5	100.00
		rv_dm_csr_hw_reset	2.860s	373.609us	5	5	100.00
		rv_dm_csr_rw	2.590s	222.247us	20	20	100.00
		rv_dm_same_csr_outstanding	8.530s	2.194ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.329m	16.691ms	5	5	100.00
		rv_dm_csr_hw_reset	2.860s	373.609us	5	5	100.00
		rv_dm_csr_rw	2.590s	222.247us	20	20	100.00
		rv_dm_same_csr_outstanding	8.530s	2.194ms	20	20	100.00
V2		TOTAL			235	251	93.63
V2S	tl_intg_err	rv_dm_sec_cm	3.050s	721.571us	5	5	100.00
		rv_dm_tl_intg_err	24.940s	4.209ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.940s	4.209ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	8.260s	2.968ms	2	2	100.00
		rv_dm_debug_disabled	0.890s	79.130us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	21.680m	821.433ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			443	462	95.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	26	96.30
V2	19	19	18	94.74
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.97	95.72	83.72	89.91	75.00	88.00	98.53	56.89

Failure Buckets

UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 9 failures:

Test rv_dm_stress_all has 9 failures.

0.rv_dm_stress_all.15923809682190471785317885201539348812362437139350902025692453235967701472746
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 2519410759 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 2519410759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_dm_stress_all.26309258152577013184168933656340406518231357942721889361554745622372362219561
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 782897193 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 782897193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 4 failures:

Test rv_dm_stress_all has 4 failures.

2.rv_dm_stress_all.88071567262948835325805490899050814776372624721759095560865611979552995604153
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1171268065 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (21963492 [0x14f22e4] vs 4182713060 [0xf94f22e4])
  UVM_INFO @ 1171268065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.rv_dm_stress_all.111914554553131427383298615063787560796692179024072579418714016559154812045317
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 1856727696 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (8932 [0x22e4] vs 4182713060 [0xf94f22e4])
  UVM_INFO @ 1856727696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 2 failures:

Test rv_dm_stress_all has 2 failures.

20.rv_dm_stress_all.53770371302423412416740048023252631009172934634554932123872037689704508563826
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 7757636545 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 7757636545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.rv_dm_stress_all.7041891484463526994692020916365973640927673443393146738472402784441280883746
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 790551627 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 790551627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.36982234655560355559012625569904283144763037673396996274745169239571486419617
    Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9020248004 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9020248004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 1.rv_dm_stress_all_with_rand_reset.65595500867954251718605354494676864280339361594045763962906608521711457798681
    Line 324, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8788032412 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (28 [0x1c] vs 18446744073709551615 [0xffffffffffffffff])
  UVM_INFO @ 8788032412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_dmi_reg_frontdoor.sv:83) [ftdr] timeout occurred! has 1 failures:
- Test rv_dm_jtag_dmi_csr_rw has 1 failures.
  - 3.rv_dm_jtag_dmi_csr_rw.106316711967416683051062838949476633705565326575706450365805237114811136477989
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest/run.log
```
  UVM_FATAL @ 228594213 ps: (jtag_dmi_reg_frontdoor.sv:83) [ftdr] timeout occurred!
  UVM_INFO @ 228594213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:87) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 34.rv_dm_stress_all.34103707782401830706957987942388477305473401704477635554552390769557215020368
    Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2481601426 ps: (rv_dm_ndmreset_req_vseq.sv:87) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
  UVM_INFO @ 2481601426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```