RV_DM Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 6.550s 4.274ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.680s 420.879us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.930s 561.524us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 50.800s 37.677ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.230s 402.040us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 37.410s 13.738ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 31.310s 11.810ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.434m 54.064ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 4.039m 84.195ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.650s 433.918us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.230s 203.579us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.450s 299.831us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.200s 1.433ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 4.720s 1.392ms 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.100s 2.018ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.480s 339.784us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 7.400s 2.383ms 2 2 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.650s 433.918us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.960s 637.151us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.290s 377.282us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.450s 299.831us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.920s 138.355us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.750s 335.424us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.510s 414.900us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.255m 40.764ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.266m 3.546ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.360s 355.626us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.266m 3.546ms 5 5 100.00
rv_dm_csr_rw 2.510s 414.900us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.780s 50.283us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.740s 74.840us 5 5 100.00
V1 TOTAL 174 174 100.00
V2 idcode rv_dm_smoke 6.550s 4.274ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 3.320s 1.133ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.290s 269.733us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.880s 167.592us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.650s 655.118us 2 2 100.00
V2 sba rv_dm_sba_tl_access 15.840s 5.146ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 51.610s 17.046ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 35.210s 12.828ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.205m 54.072ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.910s 96.218us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.730s 1.626ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.300s 230.506us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.530s 326.161us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.770s 7.778ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.486m 67.799ms 8 10 80.00
V2 hartsel_warl rv_dm_hartsel_warl 0.750s 82.825us 1 1 100.00
V2 stress_all rv_dm_stress_all 31.700s 11.532ms 37 50 74.00
V2 alert_test rv_dm_alert_test 1.030s 129.189us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 7.060s 4.406ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 7.060s 4.406ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.266m 3.546ms 5 5 100.00
rv_dm_csr_hw_reset 2.750s 335.424us 5 5 100.00
rv_dm_csr_rw 2.510s 414.900us 20 20 100.00
rv_dm_same_csr_outstanding 8.840s 7.734ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.266m 3.546ms 5 5 100.00
rv_dm_csr_hw_reset 2.750s 335.424us 5 5 100.00
rv_dm_csr_rw 2.510s 414.900us 20 20 100.00
rv_dm_same_csr_outstanding 8.840s 7.734ms 20 20 100.00
V2 TOTAL 236 251 94.02
V2S tl_intg_err rv_dm_sec_cm 2.180s 758.222us 5 5 100.00
rv_dm_tl_intg_err 31.550s 6.922ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 31.550s 6.922ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.730s 1.626ms 2 2 100.00
rv_dm_debug_disabled 1.120s 131.542us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 58.566m 302.235ms 8 10 80.00
V3 TOTAL 8 10 80.00
TOTAL 445 462 96.32

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 17 89.47
V2S 9 3 3 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.67 95.72 83.72 89.91 75.00 88.00 98.53 54.78

Failure Buckets

Past Results