RV_DM Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.550s	4.274ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.680s	420.879us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.930s	561.524us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	50.800s	37.677ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.230s	402.040us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	37.410s	13.738ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	31.310s	11.810ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.434m	54.064ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.039m	84.195ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.650s	433.918us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.230s	203.579us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.450s	299.831us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.200s	1.433ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	4.720s	1.392ms	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.100s	2.018ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.480s	339.784us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	7.400s	2.383ms	2	2	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.650s	433.918us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.960s	637.151us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.290s	377.282us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.450s	299.831us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.920s	138.355us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.750s	335.424us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.510s	414.900us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.255m	40.764ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.266m	3.546ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.360s	355.626us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.266m	3.546ms	5	5	100.00
		rv_dm_csr_rw	2.510s	414.900us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.780s	50.283us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.740s	74.840us	5	5	100.00
V1		TOTAL			174	174	100.00
V2	idcode	rv_dm_smoke	6.550s	4.274ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	3.320s	1.133ms	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.290s	269.733us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.880s	167.592us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.650s	655.118us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	15.840s	5.146ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	51.610s	17.046ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	35.210s	12.828ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.205m	54.072ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.910s	96.218us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.730s	1.626ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.300s	230.506us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.530s	326.161us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.770s	7.778ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	3.486m	67.799ms	8	10	80.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.750s	82.825us	1	1	100.00
V2	stress_all	rv_dm_stress_all	31.700s	11.532ms	37	50	74.00
V2	alert_test	rv_dm_alert_test	1.030s	129.189us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.060s	4.406ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.060s	4.406ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.266m	3.546ms	5	5	100.00
		rv_dm_csr_hw_reset	2.750s	335.424us	5	5	100.00
		rv_dm_csr_rw	2.510s	414.900us	20	20	100.00
		rv_dm_same_csr_outstanding	8.840s	7.734ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.266m	3.546ms	5	5	100.00
		rv_dm_csr_hw_reset	2.750s	335.424us	5	5	100.00
		rv_dm_csr_rw	2.510s	414.900us	20	20	100.00
		rv_dm_same_csr_outstanding	8.840s	7.734ms	20	20	100.00
V2		TOTAL			236	251	94.02
V2S	tl_intg_err	rv_dm_sec_cm	2.180s	758.222us	5	5	100.00
		rv_dm_tl_intg_err	31.550s	6.922ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	31.550s	6.922ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.730s	1.626ms	2	2	100.00
		rv_dm_debug_disabled	1.120s	131.542us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	sec_cm_lc_dft_en_intersig_mubi			0	0	--
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	58.566m	302.235ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			445	462	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	17	89.47
V2S	9	3	3	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.67	95.72	83.72	89.91	75.00	88.00	98.53	54.78

Failure Buckets

UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 10 failures:

Test rv_dm_stress_all has 10 failures.

4.rv_dm_stress_all.104296909088892725623629022218226799741380861635562381182520642849599179140809
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 5255319902 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 5255319902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.rv_dm_stress_all.88984238289684942421639119618176754545779275836516972631263213158064680501667
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log

  UVM_ERROR @ 430544226 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
  UVM_INFO @ 430544226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 2 failures:
- Test rv_dm_tap_fsm_rand_reset has 2 failures.
  - 0.rv_dm_tap_fsm_rand_reset.90086612034165472949018535236571691439257240938959201041542409176893399287224
    Line 280, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 10453360905 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 10453360905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_tap_fsm_rand_reset.67153635097031762200770898262194846597222993813857807263496349884697256805008
    Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 18127955491 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 18127955491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:839) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 2.rv_dm_stress_all_with_rand_reset.100699971678545242213059073025200128462431807136242983019287675155517728389619
    Line 587, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26338218735 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26338218735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.rv_dm_stress_all_with_rand_reset.96039842178061091501970072579046939858903483632425457449063570029112792549087
    Line 707, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63692995612 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 63692995612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 31.rv_dm_stress_all.25554356881440437125094098804030639689124891218913146227016001310194622948413
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 2815969408 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (536870920 [0x20000008] vs 1435783844 [0x559452a4])
  UVM_INFO @ 2815969408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 33.rv_dm_stress_all.93795739461766559225339693519542232591665647247214164991179354472939995180733
    Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 5044258075 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @ 5044258075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_smoke_vseq.sv:46) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all has 1 failures.
  - 35.rv_dm_stress_all.28834260860418712761502004033235737117065132788042293298010312798462465887360
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log
```
  UVM_ERROR @ 1040182859 ps: (rv_dm_smoke_vseq.sv:46) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1040182859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```