eca25c0ff8
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 2.310s | 610.661us | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.100s | 599.681us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 2.420s | 880.205us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 53.940s | 21.807ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.240s | 1.157ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 8.920s | 3.336ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 21.990s | 7.706ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 6.723m | 168.486ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 5.456m | 115.616ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.720s | 386.299us | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.990s | 184.842us | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.950s | 765.745us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 13.890s | 5.023ms | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.110s | 505.257us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.900s | 1.528ms | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.080s | 260.953us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 2.340s | 1.586ms | 2 | 2 | 100.00 |
V1 | progbuf_busy | rv_dm_cmderr_busy | 1.720s | 386.299us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.080s | 161.025us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.700s | 758.503us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.950s | 765.745us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.990s | 91.942us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 3.170s | 419.287us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.590s | 177.316us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.436m | 73.065ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.234m | 4.020ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 4.980s | 504.843us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.234m | 4.020ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.590s | 177.316us | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.940s | 111.696us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.910s | 87.634us | 5 | 5 | 100.00 |
V1 | TOTAL | 174 | 174 | 100.00 | |||
V2 | idcode | rv_dm_smoke | 2.310s | 610.661us | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 6.890s | 2.279ms | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.100s | 154.987us | 2 | 2 | 100.00 |
V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.700s | 443.401us | 2 | 2 | 100.00 |
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.090s | 517.278us | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 28.640s | 9.862ms | 20 | 20 | 100.00 |
rv_dm_delayed_resp_sba_tl_access | 30.770s | 10.697ms | 20 | 20 | 100.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 13.690s | 4.827ms | 20 | 20 | 100.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 4.788m | 105.532ms | 20 | 20 | 100.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.040s | 633.645us | 2 | 2 | 100.00 |
V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 7.440s | 5.491ms | 2 | 2 | 100.00 |
V2 | ndmreset_req | rv_dm_ndmreset_req | 1.640s | 750.082us | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 1.630s | 359.291us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 7.170s | 8.727ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 4.210m | 51.405ms | 9 | 10 | 90.00 | ||
V2 | hartsel_warl | rv_dm_hartsel_warl | 0.850s | 87.461us | 1 | 1 | 100.00 |
V2 | stress_all | rv_dm_stress_all | 37.020s | 14.994ms | 35 | 50 | 70.00 |
V2 | alert_test | rv_dm_alert_test | 1.110s | 160.685us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.450s | 293.482us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.450s | 293.482us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.234m | 4.020ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 3.170s | 419.287us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.590s | 177.316us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.130s | 577.516us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.234m | 4.020ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 3.170s | 419.287us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.590s | 177.316us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.130s | 577.516us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 235 | 251 | 93.63 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 2.260s | 785.325us | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 34.830s | 6.564ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 34.830s | 6.564ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 7.440s | 5.491ms | 2 | 2 | 100.00 |
rv_dm_debug_disabled | 0.990s | 67.756us | 2 | 2 | 100.00 | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 27 | 27 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 20.961m | 337.959ms | 7 | 10 | 70.00 |
V3 | TOTAL | 7 | 10 | 70.00 | |||
TOTAL | 443 | 462 | 95.89 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 27 | 27 | 27 | 100.00 |
V2 | 19 | 19 | 17 | 89.47 |
V2S | 9 | 3 | 3 | 33.33 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
83.34 | 95.72 | 83.72 | 89.91 | 75.00 | 88.00 | 98.21 | 52.77 |
UVM_ERROR (rv_dm_scoreboard.sv:101) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*])
has 9 failures:
4.rv_dm_stress_all.87532088420422529104708574524995839979271813947297105320154852832927098460809
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1152222508 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
UVM_INFO @ 1152222508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all.54044982629644338058702987139242941696845125386343454680768805380573730595130
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4881037634 ps: (rv_dm_scoreboard.sv:101) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (549755813896 [0x8000000008] vs 4209 [0x1071])
UVM_INFO @ 4881037634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
has 4 failures:
3.rv_dm_stress_all.7562914893060132809525167053126843705882267399923560067372046715320275321815
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2733199386 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 2733199386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all.25875225184801694045039086427924290695091517420514241860708850150425727856095
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1982067179 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 1982067179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use)
has 1 failures:
2.rv_dm_tap_fsm_rand_reset.37165632653429729890102222333673760418624536840428660788043568666654711991609
Line 351, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 33866480827 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
UVM_INFO @ 33866480827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:839) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 1 failures:
4.rv_dm_stress_all_with_rand_reset.52259376187150817711066410808144924308677451632165244821741917282107793208106
Line 466, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 60927029957 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 60927029957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:31) [rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (* [*] vs * [*])
has 1 failures:
6.rv_dm_stress_all_with_rand_reset.94852444858484411913342420553831470125668574959293824740686317811934318786585
Line 294, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4984152632 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed !wdata == get_field_val(jtag_dmi_ral.dmstatus.anyresumeack, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4984152632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 1 failures:
9.rv_dm_stress_all_with_rand_reset.4204755024476691267866449595771162016578333140978544845997036084576901872658
Line 313, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5276746499 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (6 [0x6] vs 18446744073709551615 [0xffffffffffffffff])
UVM_INFO @ 5276746499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:90) [scoreboard] Check failed item.dout[*:*] == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*])
has 1 failures:
12.rv_dm_stress_all.111614815170633032585298767798168042598685644115742812058803179485592677032108
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 623470659 ps: (rv_dm_scoreboard.sv:90) [uvm_test_top.env.scoreboard] Check failed item.dout[31:0] == selected_dtm_csr.get_mirrored_value() (108927 [0x1a97f] vs 4111444351 [0xf50fa97f])
UVM_INFO @ 623470659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:87) [rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
has 1 failures:
26.rv_dm_stress_all.28415841879457953061131405225635691342613553027102492765222686963946508190392
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14994486978 ps: (rv_dm_ndmreset_req_vseq.sv:87) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed (cfg.rv_dm_vif.cb.ndmreset_req)
UVM_INFO @ 14994486978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---