RV_DM Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.790s 823.091us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.400s 443.998us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.350s 1.031ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 46.620s 16.042ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.460s 272.738us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.070s 7.550ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 37.040s 14.727ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.956m 71.588ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.143m 23.047ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.080s 384.355us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.890s 855.779us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.430s 281.543us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.150s 1.198ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.970s 230.377us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.060s 567.687us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.030s 301.173us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.140s 1.425ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.080s 384.355us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.990s 232.429us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.750s 1.233ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.430s 281.543us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.030s 128.265us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.430s 410.542us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.740s 1.622ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.254m 17.275ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.260m 14.001ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.680s 505.648us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.260m 14.001ms 5 5 100.00
rv_dm_csr_rw 2.740s 1.622ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.820s 74.970us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.940s 107.421us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 2.790s 823.091us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.750s 653.837us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.030s 120.588us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.020s 135.061us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 5.910s 2.117ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 36.940s 13.297ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 40.140s 13.574ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 33.160s 15.879ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 3.666m 87.721ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.290s 507.893us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.780s 3.807ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.620s 328.567us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.450s 1.135ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.670s 7.549ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 6.080m 31.649ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 1.510s 308.083us 1 1 100.00
V2 stress_all rv_dm_stress_all 28.720s 10.567ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.080s 148.283us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.340s 1.088ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.340s 1.088ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.260m 14.001ms 5 5 100.00
rv_dm_csr_hw_reset 3.430s 410.542us 5 5 100.00
rv_dm_csr_rw 2.740s 1.622ms 20 20 100.00
rv_dm_same_csr_outstanding 8.050s 675.902us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.260m 14.001ms 5 5 100.00
rv_dm_csr_hw_reset 3.430s 410.542us 5 5 100.00
rv_dm_csr_rw 2.740s 1.622ms 20 20 100.00
rv_dm_same_csr_outstanding 8.050s 675.902us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 4.560s 2.945ms 5 5 100.00
rv_dm_tl_intg_err 25.310s 2.925ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 25.310s 2.925ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.780s 3.807ms 2 2 100.00
rv_dm_debug_disabled 1.030s 122.575us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 5.780s 3.807ms 2 2 100.00
rv_dm_debug_disabled 1.030s 122.575us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.790s 823.091us 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 41.877m 405.999ms 10 10 100.00
V3 TOTAL 10 10 100.00
TOTAL 468 468 100.00

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.71 96.18 85.48 89.91 71.25 88.33 98.53 56.31

Past Results