RV_DM Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: fdfa12db04

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.170s	4.013ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.410s	258.973us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.810s	909.161us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	40.830s	16.112ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.270s	2.224ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	39.950s	15.918ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	31.930s	12.919ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.219m	96.525ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.679m	220.142ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.140s	259.956us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.760s	450.649us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.140s	190.549us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	4.620s	1.508ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.970s	440.722us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.550s	990.383us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.870s	287.686us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.460s	1.370ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.140s	259.956us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.930s	168.602us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.240s	195.917us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.140s	190.549us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.970s	88.281us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.070s	281.686us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.570s	162.211us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.283m	36.636ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.480m	42.607ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.960s	173.839us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.480m	42.607ms	5	5	100.00
		rv_dm_csr_rw	2.570s	162.211us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.800s	94.406us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.840s	137.915us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.170s	4.013ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.610s	311.176us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.280s	760.648us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.200s	580.994us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.390s	302.065us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	24.090s	13.867ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	26.390s	9.351ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	29.020s	10.509ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.622m	32.288ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.830s	146.387us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.770s	4.765ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.000s	106.319us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.300s	1.290ms	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	17.860s	6.716ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	9.226m	71.282ms	9	10	90.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.920s	252.923us	1	1	100.00
V2	stress_all	rv_dm_stress_all	45.920s	20.389ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.060s	152.088us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.200s	2.486ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.200s	2.486ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.480m	42.607ms	5	5	100.00
		rv_dm_csr_hw_reset	3.070s	281.686us	5	5	100.00
		rv_dm_csr_rw	2.570s	162.211us	20	20	100.00
		rv_dm_same_csr_outstanding	8.070s	2.071ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.480m	42.607ms	5	5	100.00
		rv_dm_csr_hw_reset	3.070s	281.686us	5	5	100.00
		rv_dm_csr_rw	2.570s	162.211us	20	20	100.00
		rv_dm_same_csr_outstanding	8.070s	2.071ms	20	20	100.00
V2		TOTAL			250	251	99.60
V2S	tl_intg_err	rv_dm_sec_cm	2.420s	568.234us	5	5	100.00
		rv_dm_tl_intg_err	29.430s	5.083ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	29.430s	5.083ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.770s	4.765ms	2	2	100.00
		rv_dm_debug_disabled	1.060s	111.660us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.770s	4.765ms	2	2	100.00
		rv_dm_debug_disabled	1.060s	111.660us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.170s	4.013ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	36.717m	490.712ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			467	468	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	18	94.74
V2S	7	3	3	42.86
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.83	96.18	85.34	89.91	72.50	88.33	98.21	56.31

Failure Buckets

• UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
  • Test rv_dm_tap_fsm_rand_reset has 1 failures.

    • 6.rv_dm_tap_fsm_rand_reset.2657232400030226376981297375359075473239942922480607285887771531005695346687
      Line 329, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log

        UVM_FATAL @ 24660144099 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
        UVM_INFO @ 24660144099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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