RV_DM Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: e9b7e615a7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.590s 2.276ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.310s 523.044us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.310s 632.142us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.781m 41.740ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.980s 476.380us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 24.800s 9.677ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 29.310s 10.666ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.950m 43.767ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 9.517m 241.795ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 3.030s 857.425us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.160s 196.736us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 0.990s 113.984us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.310s 2.268ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.360s 497.939us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.080s 286.426us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.740s 184.402us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.920s 841.075us 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 3.030s 857.425us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.950s 186.017us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.450s 1.273ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.990s 113.984us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.890s 204.053us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.370s 225.372us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.790s 280.848us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.210m 6.658ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.366m 13.419ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 5.150s 470.419us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.366m 13.419ms 5 5 100.00
rv_dm_csr_rw 2.790s 280.848us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.030s 146.907us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.780s 32.103us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 3.590s 2.276ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.670s 353.211us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.450s 702.692us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.160s 163.816us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 5.750s 2.091ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 48.180s 16.038ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 24.140s 8.264ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 31.450s 13.327ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.314m 150.398ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.740s 430.391us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 12.240s 4.422ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.920s 425.335us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.810s 844.627us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 7.740s 9.553ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.905m 30.349ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.720s 70.672us 1 1 100.00
V2 stress_all rv_dm_stress_all 26.740s 9.457ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.040s 154.568us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.330s 296.398us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.330s 296.398us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.366m 13.419ms 5 5 100.00
rv_dm_csr_hw_reset 2.370s 225.372us 5 5 100.00
rv_dm_csr_rw 2.790s 280.848us 20 20 100.00
rv_dm_same_csr_outstanding 8.540s 548.822us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.366m 13.419ms 5 5 100.00
rv_dm_csr_hw_reset 2.370s 225.372us 5 5 100.00
rv_dm_csr_rw 2.790s 280.848us 20 20 100.00
rv_dm_same_csr_outstanding 8.540s 548.822us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 3.580s 951.722us 5 5 100.00
rv_dm_tl_intg_err 24.630s 2.762ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 24.630s 2.762ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 12.240s 4.422ms 2 2 100.00
rv_dm_debug_disabled 0.880s 61.885us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 12.240s 4.422ms 2 2 100.00
rv_dm_debug_disabled 0.880s 61.885us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.590s 2.276ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 35.761m 795.265ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 465 468 99.36

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
84.00 96.18 85.20 89.91 73.75 88.33 98.32 56.31

Failure Buckets

Past Results