V1 |
smoke |
rv_dm_smoke |
1.800s |
963.737us |
2 |
2 |
100.00 |
V1 |
jtag_dtm_csr_hw_reset |
rv_dm_jtag_dtm_csr_hw_reset |
2.310s |
561.749us |
5 |
5 |
100.00 |
V1 |
jtag_dtm_csr_rw |
rv_dm_jtag_dtm_csr_rw |
2.250s |
993.426us |
20 |
20 |
100.00 |
V1 |
jtag_dtm_csr_bit_bash |
rv_dm_jtag_dtm_csr_bit_bash |
1.991m |
41.370ms |
5 |
5 |
100.00 |
V1 |
jtag_dtm_csr_aliasing |
rv_dm_jtag_dtm_csr_aliasing |
3.070s |
988.382us |
5 |
5 |
100.00 |
V1 |
jtag_dmi_csr_hw_reset |
rv_dm_jtag_dmi_csr_hw_reset |
25.130s |
19.132ms |
5 |
5 |
100.00 |
V1 |
jtag_dmi_csr_rw |
rv_dm_jtag_dmi_csr_rw |
38.750s |
14.723ms |
20 |
20 |
100.00 |
V1 |
jtag_dmi_csr_bit_bash |
rv_dm_jtag_dmi_csr_bit_bash |
55.650s |
22.921ms |
20 |
20 |
100.00 |
V1 |
jtag_dmi_csr_aliasing |
rv_dm_jtag_dmi_csr_aliasing |
7.344m |
152.943ms |
5 |
5 |
100.00 |
V1 |
jtag_dmi_cmderr_busy |
rv_dm_cmderr_busy |
1.580s |
974.351us |
2 |
2 |
100.00 |
V1 |
jtag_dmi_cmderr_not_supported |
rv_dm_cmderr_not_supported |
1.660s |
910.739us |
2 |
2 |
100.00 |
V1 |
cmderr_exception |
rv_dm_cmderr_exception |
1.070s |
303.825us |
2 |
2 |
100.00 |
V1 |
mem_tl_access_resuming |
rv_dm_mem_tl_access_resuming |
2.000s |
867.342us |
2 |
2 |
100.00 |
V1 |
mem_tl_access_halted |
rv_dm_mem_tl_access_halted |
2.210s |
521.720us |
2 |
2 |
100.00 |
V1 |
cmderr_halt_resume |
rv_dm_cmderr_halt_resume |
7.200s |
2.225ms |
2 |
2 |
100.00 |
V1 |
dataaddr_rw_access |
rv_dm_dataaddr_rw_access |
0.880s |
186.110us |
2 |
2 |
100.00 |
V1 |
halt_resume |
rv_dm_halt_resume_whereto |
4.140s |
1.302ms |
8 |
8 |
100.00 |
V1 |
progbuf_busy |
rv_dm_cmderr_busy |
1.580s |
974.351us |
2 |
2 |
100.00 |
V1 |
abstractcmd_status |
rv_dm_abstractcmd_status |
1.000s |
112.794us |
2 |
2 |
100.00 |
V1 |
progbuf_read_write_execute |
rv_dm_progbuf_read_write_execute |
1.760s |
403.072us |
2 |
2 |
100.00 |
V1 |
progbuf_exception |
rv_dm_cmderr_exception |
1.070s |
303.825us |
2 |
2 |
100.00 |
V1 |
rom_read_access |
rv_dm_rom_read_access |
0.960s |
66.136us |
2 |
2 |
100.00 |
V1 |
csr_hw_reset |
rv_dm_csr_hw_reset |
2.530s |
504.370us |
5 |
5 |
100.00 |
V1 |
csr_rw |
rv_dm_csr_rw |
2.570s |
187.044us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
rv_dm_csr_bit_bash |
55.040s |
2.949ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
rv_dm_csr_aliasing |
1.317m |
13.397ms |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
rv_dm_csr_mem_rw_with_rand_reset |
4.880s |
491.323us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_dm_csr_aliasing |
1.317m |
13.397ms |
5 |
5 |
100.00 |
|
|
rv_dm_csr_rw |
2.570s |
187.044us |
20 |
20 |
100.00 |
V1 |
mem_walk |
rv_dm_mem_walk |
0.780s |
33.195us |
5 |
5 |
100.00 |
V1 |
mem_partial_access |
rv_dm_mem_partial_access |
1.090s |
172.814us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
180 |
180 |
100.00 |
V2 |
idcode |
rv_dm_smoke |
1.800s |
963.737us |
2 |
2 |
100.00 |
V2 |
jtag_dtm_hard_reset |
rv_dm_jtag_dtm_hard_reset |
0.940s |
101.390us |
2 |
2 |
100.00 |
V2 |
jtag_dtm_idle_hint |
rv_dm_jtag_dtm_idle_hint |
1.320s |
232.890us |
2 |
2 |
100.00 |
V2 |
jtag_dmi_failed_op |
rv_dm_dmi_failed_op |
1.550s |
302.085us |
2 |
2 |
100.00 |
V2 |
jtag_dmi_dm_inactive |
rv_dm_jtag_dmi_dm_inactive |
4.110s |
1.332ms |
2 |
2 |
100.00 |
V2 |
sba |
rv_dm_sba_tl_access |
14.290s |
8.731ms |
20 |
20 |
100.00 |
|
|
rv_dm_delayed_resp_sba_tl_access |
36.330s |
13.619ms |
20 |
20 |
100.00 |
V2 |
bad_sba |
rv_dm_bad_sba_tl_access |
45.930s |
14.805ms |
20 |
20 |
100.00 |
V2 |
sba_autoincrement |
rv_dm_autoincr_sba_tl_access |
8.673m |
185.398ms |
20 |
20 |
100.00 |
V2 |
jtag_dmi_debug_disabled |
rv_dm_jtag_dmi_debug_disabled |
1.500s |
314.991us |
2 |
2 |
100.00 |
V2 |
sba_debug_disabled |
rv_dm_sba_debug_disabled |
4.390s |
1.708ms |
2 |
2 |
100.00 |
V2 |
ndmreset_req |
rv_dm_ndmreset_req |
1.320s |
825.177us |
2 |
2 |
100.00 |
V2 |
hart_unavail |
rv_dm_hart_unavail |
3.570s |
1.073ms |
5 |
5 |
100.00 |
V2 |
tap_ctrl_transitions |
rv_dm_tap_fsm |
7.480s |
10.267ms |
1 |
1 |
100.00 |
|
|
rv_dm_tap_fsm_rand_reset |
1.842m |
52.032ms |
10 |
10 |
100.00 |
V2 |
hartsel_warl |
rv_dm_hartsel_warl |
0.850s |
72.245us |
1 |
1 |
100.00 |
V2 |
stress_all |
rv_dm_stress_all |
37.270s |
13.288ms |
50 |
50 |
100.00 |
V2 |
alert_test |
rv_dm_alert_test |
0.990s |
159.747us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
rv_dm_tl_errors |
5.440s |
230.005us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
rv_dm_tl_errors |
5.440s |
230.005us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
rv_dm_csr_aliasing |
1.317m |
13.397ms |
5 |
5 |
100.00 |
|
|
rv_dm_csr_hw_reset |
2.530s |
504.370us |
5 |
5 |
100.00 |
|
|
rv_dm_csr_rw |
2.570s |
187.044us |
20 |
20 |
100.00 |
|
|
rv_dm_same_csr_outstanding |
8.840s |
1.873ms |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
rv_dm_csr_aliasing |
1.317m |
13.397ms |
5 |
5 |
100.00 |
|
|
rv_dm_csr_hw_reset |
2.530s |
504.370us |
5 |
5 |
100.00 |
|
|
rv_dm_csr_rw |
2.570s |
187.044us |
20 |
20 |
100.00 |
|
|
rv_dm_same_csr_outstanding |
8.840s |
1.873ms |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
251 |
251 |
100.00 |
V2S |
tl_intg_err |
rv_dm_sec_cm |
2.340s |
1.287ms |
5 |
5 |
100.00 |
|
|
rv_dm_tl_intg_err |
23.030s |
7.509ms |
20 |
20 |
100.00 |
V2S |
sec_cm_bus_integrity |
rv_dm_tl_intg_err |
23.030s |
7.509ms |
20 |
20 |
100.00 |
V2S |
sec_cm_lc_hw_debug_en_intersig_mubi |
rv_dm_sba_debug_disabled |
4.390s |
1.708ms |
2 |
2 |
100.00 |
|
|
rv_dm_debug_disabled |
0.960s |
63.331us |
2 |
2 |
100.00 |
V2S |
sec_cm_lc_dft_en_intersig_mubi |
rv_dm_sba_debug_disabled |
4.390s |
1.708ms |
2 |
2 |
100.00 |
|
|
rv_dm_debug_disabled |
0.960s |
63.331us |
2 |
2 |
100.00 |
V2S |
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi |
rv_dm_smoke |
1.800s |
963.737us |
2 |
2 |
100.00 |
V2S |
sec_cm_dm_en_ctrl_lc_gated |
sec_cm_dm_en_ctrl_lc_gated |
|
|
0 |
0 |
-- |
V2S |
sec_cm_sba_tl_lc_gate_fsm_sparse |
sec_cm_sba_tl_lc_gate_fsm_sparse |
|
|
0 |
0 |
-- |
V2S |
sec_cm_mem_tl_lc_gate_fsm_sparse |
sec_cm_mem_tl_lc_gate_fsm_sparse |
|
|
0 |
0 |
-- |
V2S |
sec_cm_exec_ctrl_mubi |
sec_cm_exec_ctrl_mubi |
|
|
0 |
0 |
-- |
V2S |
|
TOTAL |
|
|
27 |
27 |
100.00 |
V3 |
stress_all_with_rand_reset |
rv_dm_stress_all_with_rand_reset |
37.464m |
1.254s |
9 |
10 |
90.00 |
V3 |
|
TOTAL |
|
|
9 |
10 |
90.00 |
|
|
TOTAL |
|
|
467 |
468 |
99.79 |