RV_DM Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	9.860s	3.712ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.310s	469.907us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.960s	498.005us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	41.440s	19.812ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.030s	1.805ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	5.780s	1.923ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	16.870s	11.833ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.731m	61.001ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.011m	92.411ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.440s	250.212us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.930s	430.884us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	0.990s	459.088us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.710s	749.178us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.870s	135.800us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.090s	460.609us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.360s	328.763us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.010s	512.064us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.440s	250.212us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.080s	550.252us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.390s	957.296us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	0.990s	459.088us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.930s	55.264us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.130s	354.250us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.450s	458.875us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.117m	5.027ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	33.230s	8.670ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.210s	413.387us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	33.230s	8.670ms	5	5	100.00
		rv_dm_csr_rw	2.450s	458.875us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.810s	58.358us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.950s	122.184us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	9.860s	3.712ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.660s	340.603us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.860s	112.977us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.360s	531.198us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.340s	433.950us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	18.920s	6.312ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	27.180s	13.015ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	20.120s	7.125ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.088m	28.393ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.010s	408.633us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	11.710s	4.395ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.940s	287.172us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	3.910s	1.185ms	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	5.990s	6.815ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	4.913m	63.523ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.920s	105.534us	1	1	100.00
V2	stress_all	rv_dm_stress_all	34.580s	12.499ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.050s	150.841us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.140s	847.260us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.140s	847.260us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	33.230s	8.670ms	5	5	100.00
		rv_dm_csr_hw_reset	3.130s	354.250us	5	5	100.00
		rv_dm_csr_rw	2.450s	458.875us	20	20	100.00
		rv_dm_same_csr_outstanding	10.880s	9.618ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	33.230s	8.670ms	5	5	100.00
		rv_dm_csr_hw_reset	3.130s	354.250us	5	5	100.00
		rv_dm_csr_rw	2.450s	458.875us	20	20	100.00
		rv_dm_same_csr_outstanding	10.880s	9.618ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	2.650s	1.125ms	5	5	100.00
		rv_dm_tl_intg_err	22.480s	2.676ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	22.480s	2.676ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	11.710s	4.395ms	2	2	100.00
		rv_dm_debug_disabled	0.900s	134.253us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	11.710s	4.395ms	2	2	100.00
		rv_dm_debug_disabled	0.900s	134.253us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	9.860s	3.712ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	38.766m	418.495ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			467	468	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	7	3	3	42.86
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.49	96.18	85.48	89.91	72.50	88.33	97.90	54.13

Failure Buckets

• UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 7.rv_dm_stress_all_with_rand_reset.12733191367891952974814877261764849553742185642890841306418872601030017304104
      Line 413, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68950989399 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 68950989399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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