RV_DM Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.580s	934.053us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.540s	334.012us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.680s	757.638us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	44.720s	15.575ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.160s	560.805us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	27.260s	10.820ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	41.780s	15.427ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.153m	43.313ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	5.466m	207.465ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.110s	641.886us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.990s	921.065us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.650s	977.426us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	7.460s	2.903ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.930s	531.149us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.300s	1.373ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.790s	83.008us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.000s	1.389ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.110s	641.886us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.000s	459.376us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.100s	525.841us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.650s	977.426us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.910s	52.012us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.610s	703.294us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.710s	230.512us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.129m	5.127ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.317m	4.699ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.530s	473.699us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.317m	4.699ms	5	5	100.00
		rv_dm_csr_rw	2.710s	230.512us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.840s	49.153us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.800s	153.693us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.580s	934.053us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.470s	316.628us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.240s	374.691us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.380s	266.886us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.540s	315.324us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	25.540s	9.633ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	19.110s	12.476ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	19.040s	5.944ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	5.235m	131.058ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.020s	384.026us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	10.230s	3.648ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.720s	355.911us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.290s	226.402us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	30.820s	10.625ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.132m	42.164ms	9	10	90.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.840s	54.966us	1	1	100.00
V2	stress_all	rv_dm_stress_all	49.510s	15.814ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.020s	128.047us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.100s	526.858us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.100s	526.858us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.317m	4.699ms	5	5	100.00
		rv_dm_csr_hw_reset	2.610s	703.294us	5	5	100.00
		rv_dm_csr_rw	2.710s	230.512us	20	20	100.00
		rv_dm_same_csr_outstanding	8.150s	610.696us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.317m	4.699ms	5	5	100.00
		rv_dm_csr_hw_reset	2.610s	703.294us	5	5	100.00
		rv_dm_csr_rw	2.710s	230.512us	20	20	100.00
		rv_dm_same_csr_outstanding	8.150s	610.696us	20	20	100.00
V2		TOTAL			250	251	99.60
V2S	tl_intg_err	rv_dm_sec_cm	2.850s	1.594ms	5	5	100.00
		rv_dm_tl_intg_err	32.050s	6.543ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	32.050s	6.543ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	10.230s	3.648ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	71.167us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	10.230s	3.648ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	71.167us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.580s	934.053us	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	34.468m	800.619ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			463	468	98.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	18	94.74
V2S	7	3	3	42.86
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.07	96.18	85.48	89.91	73.75	88.33	98.53	56.31

Failure Buckets

UVM_ERROR (rv_dm_hart_unavail_vseq.sv:22) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 2 failures:
- Test rv_dm_stress_all_with_rand_reset has 2 failures.
  - 4.rv_dm_stress_all_with_rand_reset.27056483131100422493303267096584915547153250101299801621925733394949357088517
    Line 508, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19153930120 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 19153930120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.rv_dm_stress_all_with_rand_reset.41109455576049592332235414431897817659220867457285683476777543426370031920292
    Line 307, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6540676968 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 6540676968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_dm_base_vseq.sv:290) [rv_dm_cmderr_not_supported_vseq] Check failed (!dmcontrol_val.ndmreset) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 0.rv_dm_stress_all_with_rand_reset.67883042412088291474529489298846833929854860359455152441082188488536443562886
    Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9595511695 ps: (rv_dm_base_vseq.sv:290) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed (!dmcontrol_val.ndmreset)
  UVM_INFO @ 9595511695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (jtag_driver.sv:63) [driver] Check failed (!tck_in_use) has 1 failures:
- Test rv_dm_tap_fsm_rand_reset has 1 failures.
  - 9.rv_dm_tap_fsm_rand_reset.64757118531711082320270197917704586731467788862616100116338704629823818012176
    Line 284, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest/run.log
```
  UVM_FATAL @ 5565644831 ps: (jtag_driver.sv:63) [uvm_test_top.env.m_jtag_agent.driver] Check failed (!tck_in_use)
  UVM_INFO @ 5565644831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:836) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 9.rv_dm_stress_all_with_rand_reset.1188511320872468903197654546577837502794651389860677947588812926167092181266
    Line 1030, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 275949030511 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 275949030511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_DM Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c8985d6745`