RV_DM Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.690s 1.654ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.370s 412.492us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.400s 739.469us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 11.440s 15.941ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.090s 648.064us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.730s 4.323ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 21.070s 14.681ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 3.706m 83.048ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 2.116m 48.233ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 4.490s 1.445ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.320s 397.334us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.280s 228.358us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.710s 2.371ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.970s 122.160us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.010s 651.715us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.920s 260.439us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 3.460s 1.113ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 4.490s 1.445ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.470s 250.472us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.930s 306.046us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.280s 228.358us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.830s 103.266us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.220s 441.374us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.670s 243.917us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.129m 40.899ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.479m 28.944ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.100s 365.452us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.479m 28.944ms 5 5 100.00
rv_dm_csr_rw 2.670s 243.917us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.860s 96.993us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.830s 79.715us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 1.690s 1.654ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.120s 163.016us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.010s 124.278us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.930s 485.383us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.260s 2.019ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 24.350s 8.733ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 42.250s 15.461ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 16.550s 5.966ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.287m 26.136ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.100s 553.977us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 5.940s 2.082ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.230s 175.890us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.370s 248.101us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 22.220s 8.535ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 5.927m 62.845ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.770s 116.760us 1 1 100.00
V2 stress_all rv_dm_stress_all 16.740s 5.312ms 50 50 100.00
V2 alert_test rv_dm_alert_test 0.990s 131.376us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.340s 1.033ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.340s 1.033ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.479m 28.944ms 5 5 100.00
rv_dm_csr_hw_reset 3.220s 441.374us 5 5 100.00
rv_dm_csr_rw 2.670s 243.917us 20 20 100.00
rv_dm_same_csr_outstanding 7.690s 1.128ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.479m 28.944ms 5 5 100.00
rv_dm_csr_hw_reset 3.220s 441.374us 5 5 100.00
rv_dm_csr_rw 2.670s 243.917us 20 20 100.00
rv_dm_same_csr_outstanding 7.690s 1.128ms 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 6.480s 2.259ms 5 5 100.00
rv_dm_tl_intg_err 28.500s 5.108ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 28.500s 5.108ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 5.940s 2.082ms 2 2 100.00
rv_dm_debug_disabled 0.970s 43.746us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 5.940s 2.082ms 2 2 100.00
rv_dm_debug_disabled 0.970s 43.746us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 1.690s 1.654ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 21.825m 63.133ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 465 468 99.36

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
83.86 96.18 85.48 89.91 72.50 88.33 98.32 56.31

Failure Buckets

Past Results