e4c5daa580
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 7.920s | 5.215ms | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 3.020s | 1.027ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.690s | 744.294us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 18.550s | 21.183ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 3.170s | 998.641us | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 24.150s | 8.449ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 30.270s | 9.890ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.031m | 19.981ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 4.025m | 96.108ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.370s | 457.422us | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.100s | 164.780us | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.450s | 247.792us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 3.950s | 1.120ms | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.440s | 547.871us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.610s | 700.630us | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.840s | 131.951us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 3.120s | 924.688us | 8 | 8 | 100.00 |
V1 | progbuf_busy | rv_dm_cmderr_busy | 1.370s | 457.422us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.820s | 141.320us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 1.130s | 321.384us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.450s | 247.792us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.930s | 130.623us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 3.430s | 452.608us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.830s | 226.414us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 38.650s | 41.267ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.368m | 4.709ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 4.810s | 236.036us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.368m | 4.709ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.830s | 226.414us | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.950s | 124.623us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 1.000s | 141.538us | 5 | 5 | 100.00 |
V1 | TOTAL | 180 | 180 | 100.00 | |||
V2 | idcode | rv_dm_smoke | 7.920s | 5.215ms | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.930s | 456.610us | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.420s | 238.372us | 2 | 2 | 100.00 |
V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.960s | 183.340us | 2 | 2 | 100.00 |
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 2.210s | 2.248ms | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 17.510s | 12.088ms | 20 | 20 | 100.00 |
rv_dm_delayed_resp_sba_tl_access | 34.400s | 11.879ms | 20 | 20 | 100.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 20.710s | 7.850ms | 20 | 20 | 100.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.063m | 42.346ms | 20 | 20 | 100.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.630s | 717.600us | 2 | 2 | 100.00 |
V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.680s | 1.095ms | 2 | 2 | 100.00 |
V2 | ndmreset_req | rv_dm_ndmreset_req | 1.740s | 463.171us | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 2.680s | 814.658us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 12.170s | 8.048ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 13.660m | 76.902ms | 10 | 10 | 100.00 | ||
V2 | hartsel_warl | rv_dm_hartsel_warl | 0.830s | 415.287us | 1 | 1 | 100.00 |
V2 | stress_all | rv_dm_stress_all | 24.020s | 13.185ms | 50 | 50 | 100.00 |
V2 | alert_test | rv_dm_alert_test | 1.210s | 180.981us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.110s | 426.697us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.110s | 426.697us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.368m | 4.709ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 3.430s | 452.608us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.830s | 226.414us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.060s | 1.566ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.368m | 4.709ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 3.430s | 452.608us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.830s | 226.414us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.060s | 1.566ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 251 | 251 | 100.00 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 4.410s | 1.275ms | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 32.410s | 6.610ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 32.410s | 6.610ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.680s | 1.095ms | 2 | 2 | 100.00 |
rv_dm_debug_disabled | 1.050s | 109.024us | 2 | 2 | 100.00 | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.680s | 1.095ms | 2 | 2 | 100.00 |
rv_dm_debug_disabled | 1.050s | 109.024us | 2 | 2 | 100.00 | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 7.920s | 5.215ms | 2 | 2 | 100.00 |
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 27 | 27 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 35.444m | 138.192ms | 6 | 10 | 60.00 |
V3 | TOTAL | 6 | 10 | 60.00 | |||
TOTAL | 464 | 468 | 99.15 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 27 | 27 | 27 | 100.00 |
V2 | 19 | 19 | 19 | 100.00 |
V2S | 7 | 3 | 3 | 42.86 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
83.68 | 96.18 | 84.92 | 89.91 | 73.75 | 88.33 | 98.53 | 54.13 |
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:22) [rv_dm_hart_unavail_vseq] Check failed
gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 2 failures:
0.rv_dm_stress_all_with_rand_reset.11455662082591238259821028016407746057517876160861836326192814753577188279839
Line 426, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51700429003 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51700429003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all_with_rand_reset.34729417464025514142270562183370498670027548719269822865778963566819778292017
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1779820621 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1779820621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:836) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 2 failures:
3.rv_dm_stress_all_with_rand_reset.9668321413527918040080395781650521621023220703099521520391302396779079532257
Line 407, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29150002054 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29150002054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.4958206671982421423508715971648930981225743757990188459899323427579262465718
Line 891, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 89181713873 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 89181713873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---