RV_DM Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.880s	671.180us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.570s	512.804us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.630s	1.010ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	22.480s	19.758ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.830s	1.165ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	13.530s	8.245ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	14.590s	5.455ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.361m	54.791ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.579m	109.008ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.600s	1.306ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.750s	843.175us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.260s	207.147us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.790s	3.168ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.910s	574.545us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	4.420s	1.360ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.880s	96.409us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.960s	1.103ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.600s	1.306ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.070s	574.888us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.340s	782.057us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.260s	207.147us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.860s	126.840us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.560s	433.517us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.590s	1.506ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.298m	30.244ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.248m	7.104ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.960s	182.340us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.248m	7.104ms	5	5	100.00
		rv_dm_csr_rw	2.590s	1.506ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.980s	123.802us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.830s	60.958us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	1.880s	671.180us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.220s	167.466us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.300s	242.105us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.890s	379.051us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	4.080s	1.465ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	37.860s	12.357ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	16.440s	5.703ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	25.030s	9.228ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.250m	91.709ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.120s	155.053us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.980s	2.406ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.820s	463.619us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.790s	393.909us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	20.490s	9.456ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	3.883m	48.830ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.940s	115.997us	1	1	100.00
V2	stress_all	rv_dm_stress_all	18.760s	6.163ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.140s	147.810us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.000s	1.512ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.000s	1.512ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.248m	7.104ms	5	5	100.00
		rv_dm_csr_hw_reset	2.560s	433.517us	5	5	100.00
		rv_dm_csr_rw	2.590s	1.506ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.340s	887.853us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.248m	7.104ms	5	5	100.00
		rv_dm_csr_hw_reset	2.560s	433.517us	5	5	100.00
		rv_dm_csr_rw	2.590s	1.506ms	20	20	100.00
		rv_dm_same_csr_outstanding	8.340s	887.853us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	7.630s	2.696ms	5	5	100.00
		rv_dm_tl_intg_err	28.030s	4.647ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	28.030s	4.647ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.980s	2.406ms	2	2	100.00
		rv_dm_debug_disabled	1.130s	123.313us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.980s	2.406ms	2	2	100.00
		rv_dm_debug_disabled	1.130s	123.313us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.880s	671.180us	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	20.005m	356.740ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			466	468	99.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	7	3	3	42.86
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.53	96.18	85.48	89.91	72.50	88.33	98.21	54.13

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test rv_dm_stress_all_with_rand_reset has 2 failures.

    • 6.rv_dm_stress_all_with_rand_reset.61093520530875059604052701177442184199486773652350450486303038219962522304281
      Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5912444632 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5912444632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.rv_dm_stress_all_with_rand_reset.111917235421408147792866637277159604740298243731312669812013239492829670638034
      Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2264341618 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2264341618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.06_09.35.14
• 2024.08.05_11.04.56
• 2024.08.04_06.52.52
• 2024.08.03_09.04.18
• 2024.08.02_08.17.40
• 2024.08.01_09.44.15