RV_DM Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.160s 3.494ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.620s 348.804us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.430s 745.882us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 24.360s 15.497ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.340s 973.288us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 19.580s 7.188ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 30.370s 11.968ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.581m 58.987ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 2.750m 211.880ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.040s 260.101us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.540s 630.912us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.110s 237.168us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 4.150s 1.445ms 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.490s 308.861us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.440s 1.128ms 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.300s 265.121us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.410s 1.307ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.040s 260.101us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.810s 389.424us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.270s 1.091ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.110s 237.168us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.990s 75.669us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.940s 340.306us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.550s 110.933us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.233m 6.429ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.315m 15.714ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.360s 321.436us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.315m 15.714ms 5 5 100.00
rv_dm_csr_rw 2.550s 110.933us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.040s 143.873us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.040s 141.264us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 3.160s 3.494ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.490s 482.575us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.140s 176.941us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.530s 608.316us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 3.170s 1.771ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 18.350s 6.137ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 30.010s 16.769ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 50.620s 19.701ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 4.186m 86.675ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.880s 178.446us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 6.340s 4.027ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.360s 351.814us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.910s 1.092ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 3.860s 5.158ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 4.456m 44.123ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.960s 329.963us 1 1 100.00
V2 stress_all rv_dm_stress_all 28.250s 10.203ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.030s 135.093us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.320s 350.142us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.320s 350.142us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.315m 15.714ms 5 5 100.00
rv_dm_csr_hw_reset 2.940s 340.306us 5 5 100.00
rv_dm_csr_rw 2.550s 110.933us 20 20 100.00
rv_dm_same_csr_outstanding 8.150s 1.660ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.315m 15.714ms 5 5 100.00
rv_dm_csr_hw_reset 2.940s 340.306us 5 5 100.00
rv_dm_csr_rw 2.550s 110.933us 20 20 100.00
rv_dm_same_csr_outstanding 8.150s 1.660ms 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 6.320s 2.006ms 5 5 100.00
rv_dm_tl_intg_err 29.950s 4.648ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 29.950s 4.648ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 6.340s 4.027ms 2 2 100.00
rv_dm_debug_disabled 0.940s 120.275us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 6.340s 4.027ms 2 2 100.00
rv_dm_debug_disabled 0.940s 120.275us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.160s 3.494ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 23.620m 62.713ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 465 468 99.36

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
84.61 96.32 87.13 92.10 73.75 90.44 98.53 54.00

Failure Buckets

Past Results