RV_DM Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 8.480s 5.488ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.950s 803.689us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.520s 712.996us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 30.990s 12.281ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.120s 939.751us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 43.860s 15.758ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 20.690s 12.765ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.098m 29.804ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 8.040m 212.015ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.770s 1.334ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.080s 451.279us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.210s 345.655us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.910s 795.140us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.940s 487.450us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.100s 261.450us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.140s 162.937us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 4.910s 1.497ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.770s 1.334ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.110s 559.909us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.420s 447.214us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.210s 345.655us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.910s 153.782us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.830s 585.309us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.640s 207.186us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.104m 4.941ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 33.580s 2.408ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 5.280s 405.076us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 33.580s 2.408ms 5 5 100.00
rv_dm_csr_rw 2.640s 207.186us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.010s 151.866us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.870s 92.259us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 8.480s 5.488ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.320s 893.051us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.980s 100.677us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.020s 133.969us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 5.240s 1.661ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 19.160s 6.489ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 42.110s 15.249ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 32.270s 11.991ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 6.710m 154.471ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.070s 557.629us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 8.040s 4.786ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 0.900s 137.258us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.080s 196.625us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 21.490s 7.798ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 5.429m 53.679ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.780s 91.015us 1 1 100.00
V2 stress_all rv_dm_stress_all 21.930s 13.639ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.160s 139.170us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.750s 284.539us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.750s 284.539us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 33.580s 2.408ms 5 5 100.00
rv_dm_csr_hw_reset 2.830s 585.309us 5 5 100.00
rv_dm_csr_rw 2.640s 207.186us 20 20 100.00
rv_dm_same_csr_outstanding 8.360s 646.348us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 33.580s 2.408ms 5 5 100.00
rv_dm_csr_hw_reset 2.830s 585.309us 5 5 100.00
rv_dm_csr_rw 2.640s 207.186us 20 20 100.00
rv_dm_same_csr_outstanding 8.360s 646.348us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 2.640s 2.446ms 5 5 100.00
rv_dm_tl_intg_err 24.770s 4.215ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 24.770s 4.215ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 8.040s 4.786ms 2 2 100.00
rv_dm_debug_disabled 0.980s 93.512us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 8.040s 4.786ms 2 2 100.00
rv_dm_debug_disabled 0.980s 93.512us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 8.480s 5.488ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 36.849m 381.592ms 7 10 70.00
V3 TOTAL 7 10 70.00
TOTAL 465 468 99.36

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
84.94 96.32 87.41 92.10 73.75 90.44 98.42 56.10

Failure Buckets

Past Results