07b417ef03
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 3.860s | 1.998ms | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.260s | 789.124us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 3.320s | 997.796us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 22.620s | 26.953ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.350s | 1.195ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 34.000s | 12.774ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 42.080s | 15.152ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.842m | 40.672ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 2.061m | 188.256ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 2.160s | 519.221us | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 1.010s | 132.746us | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 1.570s | 477.019us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 1.360s | 490.918us | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 2.090s | 574.952us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.060s | 753.009us | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.870s | 115.876us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 2.370s | 1.143ms | 8 | 8 | 100.00 |
V1 | progbuf_busy | rv_dm_cmderr_busy | 2.160s | 519.221us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.090s | 140.352us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.060s | 1.005ms | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 1.570s | 477.019us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 1.150s | 148.507us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.600s | 449.605us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.750s | 222.075us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.304m | 38.503ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.147m | 12.701ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 4.890s | 175.787us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.147m | 12.701ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.750s | 222.075us | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 1.050s | 147.032us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.820s | 71.688us | 5 | 5 | 100.00 |
V1 | TOTAL | 180 | 180 | 100.00 | |||
V2 | idcode | rv_dm_smoke | 3.860s | 1.998ms | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.280s | 537.607us | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.930s | 600.857us | 2 | 2 | 100.00 |
V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.740s | 311.324us | 2 | 2 | 100.00 |
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 3.820s | 1.503ms | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 37.330s | 13.783ms | 20 | 20 | 100.00 |
rv_dm_delayed_resp_sba_tl_access | 34.530s | 11.236ms | 20 | 20 | 100.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 12.520s | 4.760ms | 20 | 20 | 100.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 4.453m | 102.756ms | 20 | 20 | 100.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 1.390s | 333.274us | 2 | 2 | 100.00 |
V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 12.550s | 5.037ms | 2 | 2 | 100.00 |
V2 | ndmreset_req | rv_dm_ndmreset_req | 1.350s | 781.195us | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 3.260s | 968.168us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 19.410s | 8.404ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 3.659m | 36.016ms | 10 | 10 | 100.00 | ||
V2 | hartsel_warl | rv_dm_hartsel_warl | 0.770s | 377.192us | 1 | 1 | 100.00 |
V2 | stress_all | rv_dm_stress_all | 32.330s | 11.071ms | 50 | 50 | 100.00 |
V2 | alert_test | rv_dm_alert_test | 1.200s | 159.087us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.990s | 2.849ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.990s | 2.849ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.147m | 12.701ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.600s | 449.605us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.750s | 222.075us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.050s | 1.081ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.147m | 12.701ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.600s | 449.605us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.750s | 222.075us | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.050s | 1.081ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 251 | 251 | 100.00 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 4.840s | 1.886ms | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 24.480s | 3.132ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 24.480s | 3.132ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 12.550s | 5.037ms | 2 | 2 | 100.00 |
rv_dm_debug_disabled | 1.010s | 155.022us | 2 | 2 | 100.00 | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 12.550s | 5.037ms | 2 | 2 | 100.00 |
rv_dm_debug_disabled | 1.010s | 155.022us | 2 | 2 | 100.00 | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.860s | 1.998ms | 2 | 2 | 100.00 |
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 27 | 27 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 30.530m | 499.078ms | 7 | 10 | 70.00 |
V3 | TOTAL | 7 | 10 | 70.00 | |||
TOTAL | 465 | 468 | 99.36 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 27 | 27 | 27 | 100.00 |
V2 | 19 | 19 | 19 | 100.00 |
V2S | 7 | 3 | 3 | 42.86 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
84.59 | 96.32 | 86.85 | 92.10 | 73.75 | 90.44 | 98.53 | 54.13 |
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:22) [rv_dm_hart_unavail_vseq] Check failed
gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
5.rv_dm_stress_all_with_rand_reset.29698351799384916434905554383571189241561174738919183978539730053961720547696
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8642611910 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8642611910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:293) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 1 failures:
7.rv_dm_stress_all_with_rand_reset.55165775233413431895782991408867130541690948113017040987288089242842574072695
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2288522520 ps: (rv_dm_base_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2288522520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:33) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*])
has 1 failures:
8.rv_dm_stress_all_with_rand_reset.36978147033597109688985718860172923704391189075402095618745935968945200262750
Line 277, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2890443581 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2890443581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---