RV_DM Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.800s	1.689ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.740s	739.531us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.040s	505.977us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	52.400s	18.429ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.500s	2.109ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	11.260s	3.934ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	10.060s	13.805ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	5.891m	127.814ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.222m	92.837ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.800s	389.667us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.960s	565.329us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.480s	298.514us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.630s	2.327ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.510s	568.338us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.940s	1.538ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.970s	133.872us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.840s	1.332ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.800s	389.667us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.710s	324.803us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.080s	284.621us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.480s	298.514us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.990s	97.582us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.600s	173.193us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.840s	1.414ms	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.290m	30.564ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.352m	23.854ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.870s	123.949us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.352m	23.854ms	5	5	100.00
		rv_dm_csr_rw	2.840s	1.414ms	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.990s	121.951us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.970s	126.760us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	5.800s	1.689ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.140s	150.701us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.940s	105.444us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.040s	551.681us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.440s	987.138us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	21.160s	15.760ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	27.730s	9.166ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	29.380s	10.415ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.925m	81.837ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.480s	586.278us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.700s	4.862ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.500s	681.351us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.690s	776.900us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	13.160s	4.492ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.264m	25.979ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.790s	91.336us	1	1	100.00
V2	stress_all	rv_dm_stress_all	21.190s	6.919ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.020s	106.543us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.420s	1.521ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.420s	1.521ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.352m	23.854ms	5	5	100.00
		rv_dm_csr_hw_reset	2.600s	173.193us	5	5	100.00
		rv_dm_csr_rw	2.840s	1.414ms	20	20	100.00
		rv_dm_same_csr_outstanding	9.220s	2.831ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.352m	23.854ms	5	5	100.00
		rv_dm_csr_hw_reset	2.600s	173.193us	5	5	100.00
		rv_dm_csr_rw	2.840s	1.414ms	20	20	100.00
		rv_dm_same_csr_outstanding	9.220s	2.831ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.790s	1.408ms	5	5	100.00
		rv_dm_tl_intg_err	28.810s	4.555ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	28.810s	4.555ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.700s	4.862ms	2	2	100.00
		rv_dm_debug_disabled	0.890s	307.227us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.700s	4.862ms	2	2	100.00
		rv_dm_debug_disabled	0.890s	307.227us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	5.800s	1.689ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	18.110m	392.389ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			463	468	98.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	7	3	3	42.86
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.69	96.32	86.85	92.10	72.50	90.44	98.32	56.31

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test rv_dm_stress_all_with_rand_reset has 3 failures.
  - 0.rv_dm_stress_all_with_rand_reset.15260723645181449930973981871639094513845519737151667897926855733834422929084
    Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1506923483 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1506923483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rv_dm_stress_all_with_rand_reset.3483166399971308571253240404733809829002726012564748207371736685013932907247
    Line 492, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52120451712 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 52120451712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (rv_dm_cmderr_not_supported_vseq.sv:26) [rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (* [*] vs * [*]) has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 2.rv_dm_stress_all_with_rand_reset.1603174950715850385307029145480832842448896859388463399936226406012939077365
    Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3844063269 ps: (rv_dm_cmderr_not_supported_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed abstractcs.cmderr == cmderr_exp (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3844063269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [rv_dm_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rv_dm_stress_all_with_rand_reset has 1 failures.
  - 8.rv_dm_stress_all_with_rand_reset.52614470130716770951793700144655720962549980749968304143295787074593437007438
    Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17630524618 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Timeout waiting tl_access : addr=0x4a14a348
  UVM_INFO @ 17630524618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_DM Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`