RV_DM Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.440s 1.269ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.480s 296.203us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.820s 936.064us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 29.480s 17.948ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.110s 1.472ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 12.680s 4.175ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 37.390s 13.436ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.952m 70.881ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 4.772m 104.699ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 4.210s 1.327ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.630s 373.978us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.690s 475.536us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.460s 703.455us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.950s 204.047us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.040s 544.588us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.800s 283.272us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.060s 489.667us 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 4.210s 1.327ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.870s 186.022us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.760s 1.298ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.690s 475.536us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.110s 148.729us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.760s 260.764us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.580s 135.785us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.257m 7.559ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.365m 19.412ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.760s 458.683us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.365m 19.412ms 5 5 100.00
rv_dm_csr_rw 2.580s 135.785us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.800s 60.280us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.820s 152.463us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 2.440s 1.269ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.730s 723.874us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.510s 331.954us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.270s 475.798us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.540s 367.586us 2 2 100.00
V2 sba rv_dm_sba_tl_access 18.970s 6.574ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 21.960s 17.725ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 41.470s 15.467ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.429m 65.346ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.500s 699.567us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.080s 821.294us 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.110s 266.747us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 2.140s 1.022ms 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 14.120s 5.266ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 3.025m 26.230ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 1.240s 226.199us 1 1 100.00
V2 stress_all rv_dm_stress_all 45.290s 16.411ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.020s 122.660us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.480s 2.403ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.480s 2.403ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.365m 19.412ms 5 5 100.00
rv_dm_csr_hw_reset 2.760s 260.764us 5 5 100.00
rv_dm_csr_rw 2.580s 135.785us 20 20 100.00
rv_dm_same_csr_outstanding 8.480s 644.650us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.365m 19.412ms 5 5 100.00
rv_dm_csr_hw_reset 2.760s 260.764us 5 5 100.00
rv_dm_csr_rw 2.580s 135.785us 20 20 100.00
rv_dm_same_csr_outstanding 8.480s 644.650us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 2.890s 706.403us 5 5 100.00
rv_dm_tl_intg_err 29.340s 5.218ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 29.340s 5.218ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.080s 821.294us 2 2 100.00
rv_dm_debug_disabled 1.160s 138.145us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.080s 821.294us 2 2 100.00
rv_dm_debug_disabled 1.160s 138.145us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.440s 1.269ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 27 27 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 32.748m 887.568ms 5 10 50.00
V3 TOTAL 5 10 50.00
TOTAL 463 468 98.93

Testplan Progress

Items Total Written Passing Progress
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 7 3 3 42.86
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
84.91 96.32 87.13 92.10 73.75 90.44 98.42 56.19

Failure Buckets

Past Results