RV_DM Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.430s	1.236ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.330s	905.977us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.620s	1.164ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	28.040s	20.333ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.560s	653.616us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	24.070s	9.011ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	33.990s	12.486ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.182m	72.832ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.949m	110.367ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.310s	1.005ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.390s	287.156us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	0.960s	120.812us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.940s	179.905us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.490s	589.265us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.210s	242.253us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.940s	154.993us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.960s	819.884us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	3.310s	1.005ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.190s	135.107us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.810s	871.969us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	0.960s	120.812us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.870s	75.190us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.640s	569.610us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.740s	413.829us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.099m	5.142ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.372m	55.041ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.870s	249.841us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.372m	55.041ms	5	5	100.00
		rv_dm_csr_rw	2.740s	413.829us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.790s	73.454us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.880s	81.465us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	2.430s	1.236ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.810s	843.651us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.610s	323.185us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.800s	160.999us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.230s	480.646us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	2.750s	741.609us	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	2.800s	765.055us	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	3.280s	942.095us	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.760s	1.545ms	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.010s	538.263us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	12.370s	4.792ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.320s	310.151us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.480s	1.024ms	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.600s	4.060ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	41.870s	16.638ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.900s	387.099us	1	1	100.00
V2	stress_all	rv_dm_stress_all	34.800s	12.296ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.130s	174.839us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.360s	615.163us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.360s	615.163us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.372m	55.041ms	5	5	100.00
		rv_dm_csr_hw_reset	2.640s	569.610us	5	5	100.00
		rv_dm_csr_rw	2.740s	413.829us	20	20	100.00
		rv_dm_same_csr_outstanding	7.710s	3.738ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.372m	55.041ms	5	5	100.00
		rv_dm_csr_hw_reset	2.640s	569.610us	5	5	100.00
		rv_dm_csr_rw	2.740s	413.829us	20	20	100.00
		rv_dm_same_csr_outstanding	7.710s	3.738ms	20	20	100.00
V2		TOTAL			171	251	68.13
V2S	tl_intg_err	rv_dm_sec_cm	3.150s	873.702us	5	5	100.00
		rv_dm_tl_intg_err	29.730s	6.200ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	29.730s	6.200ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	12.370s	4.792ms	2	2	100.00
		rv_dm_debug_disabled	1.080s	110.881us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	12.370s	4.792ms	2	2	100.00
		rv_dm_debug_disabled	1.080s	110.881us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	2.430s	1.236ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.840s	383.143us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			37	37	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.387m	91.882ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			394	478	82.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	15	78.95
V2S	7	4	4	57.14
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.79	96.02	86.85	91.55	75.64	89.08	98.42	55.97

Failure Buckets

• UVM_ERROR (rv_dm_scoreboard.sv:199) [scoreboard] Check failed (sba_tl_access_q.size() == *) has 80 failures:

  • Test rv_dm_sba_tl_access has 20 failures.

    • 0.rv_dm_sba_tl_access.68890468582484920057251338520795905436295454648843448065092192062230874296071
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_ERROR @ 146459294 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 146459294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_sba_tl_access.26535887944649608598887516747877555347271853791509821892948757776965176807532
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log

        UVM_ERROR @ 141523465 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 141523465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_delayed_resp_sba_tl_access has 20 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.28770924887246106172642194147929481320498559728154161976438941284068743599946
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_ERROR @ 110132548 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 110132548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_delayed_resp_sba_tl_access.96512672907178061652501849730934617991929042673989186538287323724262233976277
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_ERROR @ 118618361 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 118618361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_bad_sba_tl_access has 20 failures.

    • 0.rv_dm_bad_sba_tl_access.59654734153681229326729340797903073321468728515040006639304979337867265189174
      Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_ERROR @ 172812485 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 172812485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_bad_sba_tl_access.94698575726056100804538089987697355120176249496481730799932676076810202969669
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_ERROR @ 555380643 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 555380643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_autoincr_sba_tl_access has 20 failures.

    • 0.rv_dm_autoincr_sba_tl_access.77996940384361848558850973429314132309265465067312285146002246047680659684010
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_ERROR @ 416959453 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @ 416959453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_autoincr_sba_tl_access.109878601017736564147691460744575802032424599579893495187275042425598540340899
      Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_ERROR @  66972433 ps: (rv_dm_scoreboard.sv:199) [uvm_test_top.env.scoreboard] Check failed (sba_tl_access_q.size() == 0)
        UVM_INFO @  66972433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_vseq.sv:848) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.4860539978958686035177118974519071371252405832708988966384796546413067908611
      Line 273, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1714905586 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1714905586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_base_vseq.sv:290) [rv_dm_mem_tl_access_resuming_vseq] Check failed (!dmcontrol_val.ndmreset) has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 5.rv_dm_stress_all_with_rand_reset.81068431543249935758949291452881849399686099032500615412100804572080457674925
      Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7372796998 ps: (rv_dm_base_vseq.sv:290) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed (!dmcontrol_val.ndmreset)
        UVM_INFO @ 7372796998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:29) [rv_dm_mem_tl_access_resuming_vseq] Check failed reg_status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 6.rv_dm_stress_all_with_rand_reset.88228866901283272605072590504105396999125590246261446441746122876750116368686
      Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1330332706 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:29) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed reg_status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1330332706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:51) [rv_dm_mem_tl_access_resuming_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 9.rv_dm_stress_all_with_rand_reset.104075718222174084764228273254690082125857909522281080269912039480504164727943
      Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 781418082 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:51) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 781418082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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